This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
eparate patch for updating MAINTAINERS file
Anup Patel (15):
RISC-V: Add bitmap reprensenting ISA features common across CPUs
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy functions
RISC-V: K
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
ine.
The one thing which two-staged page tables missed was to
remove use of early_init_fdt_reserve_self() which is what
this patch does.
Also, the ARM64 Linux also used FIXMAP to map FDT and
it does not use early_init_fdt_reserve_self() to reserved FDT.
Anyways, my comments to previous version
K0xff
> +
> +/* SBI return error codes */
> +#define SBI_SUCCESS0
> +#define SBI_ERR_FAILURE-1
> +#define SBI_ERR_NOT_SUPPORTED -2
> +#define SBI_ERR_INVALID_PARAM -3
> +#define SBI_ERR_DENIED -4
> +#define SBI_ERR_INVALID_ADDRESS -5
> +
> +#endif
> --
> 2.21.0
>
Thanks for considering KVM user-space SBI emulation.
Reviewed-by: Anup Patel
Regards,
Anup
eturn ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +
> +static long sbi_get_firmware_version(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_IMP_VERSION,
> + 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +
> +void sbi_init(void)
> +{
> + int ret;
> +
> + ret = sbi_get_spec_version();
> + if (ret > 0)
> + sbi_spec_version = ret;
> +
> + pr_info("SBI specification v%lu.%lu detected\n",
> + sbi_major_version(), sbi_minor_version());
> + if (!sbi_spec_is_0_1())
> + pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> + sbi_get_firmware_id(), sbi_get_firmware_version());
> +}
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index a990a6cb184f..abf2b9ee5307 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -21,6 +21,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -70,6 +71,7 @@ void __init setup_arch(char **cmdline_p)
> swiotlb_init(1);
> #endif
>
> + sbi_init();
We should do sbi_init() as early as possible.
Probably just after parse_early_param() in setup_arch().
> #ifdef CONFIG_SMP
> setup_smp();
> #endif
> --
> 2.21.0
>
Just a small comment above otherwise looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
unsigned long size,
> unsigned long asid)
> {
> - SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> + SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> + start, size, asid);
> }
>
> #endif
> --
> 2.21.0
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
We have Goldfish RTC device available on QEMU RISC-V virt machine
hence enable required driver in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 3 +++
arch/riscv/configs/rv32_defconfig | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch
We don't need explicit dependency of Goldfish kconfig option on various
architectures. Instead, the Goldfish kconfig option should only depend
on HAS_IOMEM and HAS_DMA which is sufficient for all Goldfish devices.
Signed-off-by: Anup Patel
---
drivers/platform/goldfish/Kconfig | 3 +--
1 file
For the QEMU patches adding Goldfish RTC to virt machine refer:
https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg05465.html
Changes since v1:
- Updated PATCH1 to allow goldfish drivers for all archs with IOMEM
and DMA support
Anup Patel (2):
platform: goldfish: Allow goldfish
On Wed, Sep 25, 2019 at 10:37 AM Greg Kroah-Hartman
wrote:
>
> On Wed, Sep 25, 2019 at 10:30:00AM +0530, Anup Patel wrote:
> > On Wed, Sep 25, 2019 at 10:13 AM Greg Kroah-Hartman
> > wrote:
> > >
> > > On Wed, Sep 25, 2019 at 04:30:03AM +, Anup Patel
On Wed, Sep 25, 2019 at 10:13 AM Greg Kroah-Hartman
wrote:
>
> On Wed, Sep 25, 2019 at 04:30:03AM +, Anup Patel wrote:
> > We will be using some of the Goldfish virtual platform devices (such
> > as RTC) on QEMU RISC-V virt machine so this patch enables goldfish
> > k
For the QEMU patches adding Goldfish RTC to virt machine refer:
https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg05465.html
Anup Patel (2):
platform: goldfish: Allow goldfish virtual platform drivers for RISCV
RISC-V: defconfig: Enable Goldfish RTC driver
arch/riscv/configs
We have Goldfish RTC device available on QEMU RISC-V virt machine
hence enable required driver in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 3 +++
arch/riscv/configs/rv32_defconfig | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch
We will be using some of the Goldfish virtual platform devices (such
as RTC) on QEMU RISC-V virt machine so this patch enables goldfish
kconfig option for RISC-V architecture.
Signed-off-by: Anup Patel
---
drivers/platform/goldfish/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On Mon, Sep 23, 2019 at 7:03 PM Paolo Bonzini wrote:
>
> On 23/09/19 15:09, Anup Patel wrote:
> >>> +#ifndef CONFIG_RISCV_ISA_C
> >>> + "li %[tilen], 4\n"
> >>> +#else
> >>> + "li %[ti
On Mon, Sep 23, 2019 at 4:42 PM Paolo Bonzini wrote:
>
> On 04/09/19 18:15, Anup Patel wrote:
> > + unsigned long guest_sstatus =
> > + vcpu->arch.guest_context.sstatus | SR_MXR;
> > + unsigned long guest_hstatus =
>
On Mon, Sep 23, 2019 at 12:31 PM Alexander Graf wrote:
>
>
>
> On 04.09.19 18:16, Anup Patel wrote:
> > From: Atish Patra
> >
> > The KVM host kernel running in HS-mode needs to handle SBI calls coming
> > from guest kernel running in VS-mode.
> >
> &
On Mon, Sep 23, 2019 at 12:24 PM Alexander Graf wrote:
>
>
>
> On 04.09.19 18:15, Anup Patel wrote:
> > We get illegal instruction trap whenever Guest/VM executes WFI
> > instruction.
> >
> > This patch handles WFI trap by blocking the trapped VCPU using
> &
On Mon, Sep 23, 2019 at 12:14 PM Alexander Graf wrote:
>
>
>
> On 04.09.19 18:14, Anup Patel wrote:
> > This patch implements VCPU create, init and destroy functions
> > required by generic KVM module. We don't have much dynamic
> > resources in struct kvm_vcpu_arc
On Wed, Sep 4, 2019 at 9:44 PM Anup Patel wrote:
>
> For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
> VCPU config and registers from user-space.
>
> We have three types of VCPU registers:
> 1. CONFIG - these are VCPU config and capabilities
> 2. CO
On Sat, Sep 21, 2019 at 3:31 PM Paul Walmsley wrote:
>
> Hi Anup,
>
> Thanks for changing this to use a bitmap. A few comments below -
>
> On Wed, 4 Sep 2019, Anup Patel wrote:
>
> > This patch adds riscv_isa bitmap which represents Host ISA features
>
rvation */
> + __dtb_pa = dtb_pa;
> }
>
> static void __init setup_vm_final(void)
> --
> 2.7.4
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
This deserves to be stable kernel fix as well.
You should add:
Cc: sta...@vger.kernel.org
in your commit description.
Apart from minor nits above.
Reviewed-by: Anup Patel
I tried this patch for both RV64 and RV32 on QEMU with
Yocto rootfs.
Tested-by: Anup Patel
Regards,
Anup
Hi Paul,
On Wed, Sep 4, 2019 at 9:43 PM Anup Patel wrote:
>
> This patch adds riscv_isa bitmap which represents Host ISA features
> common across all Host CPUs. The riscv_isa is not same as elf_hwcap
> because elf_hwcap will only have ISA features relevant for user-space
> apps wh
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Paul Walmsley
> Sent: Thursday, September 19, 2019 3:56 PM
> To: Xiang Wang
> Cc: pal...@sifive.com; a...@eecs.berkeley.edu; linux-
> ri...@lists.infradead.org;
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Palmer Dabbelt
> Sent: Saturday, September 14, 2019 6:30 PM
> To: m...@aurabindo.in
> Cc: Troy Benjegerdes ; Paul Walmsley
> ; a...@eecs.berkeley.edu; linux-
> ri...@lists.infradead.org;
t; li a2, 1
> @@ -154,9 +159,6 @@ relocate:
>
> .Lsecondary_start:
> #ifdef CONFIG_SMP
> - li a1, CONFIG_NR_CPUS
> - bgeu a0, a1, .Lsecondary_park
> -
> /* Set trap vector to spin forever to help debug */
> la a3, .Lsecondary_park
> csrw CSR_STVEC, a3
> --
> 2.20.1
>
>
>
>
>
>
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Sep 6, 2019 at 2:46 PM Chester Lin wrote:
>
> Hi Anup,
>
> On Fri, Sep 06, 2019 at 01:50:37PM +0530, Anup Patel wrote:
> > On Fri, Sep 6, 2019 at 12:50 PM Chester Lin wrote:
> > >
> > > Change the symbol from "RISCV" to "RSCV&q
On Fri, Sep 6, 2019 at 12:50 PM Chester Lin wrote:
>
> Change the symbol from "RISCV" to "RSCV" so the magic number can be 32-bit
> long, which is consistent with other architectures.
>
> Signed-off-by: Chester Lin
> ---
> arch/riscv/include/asm/image.h | 9 +
> arch/riscv/kernel/head.S
On Wed, Sep 4, 2019 at 9:43 PM Anup Patel wrote:
>
> DO NOT UPSTREAM !
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/configs/defconfig | 2 ++
> arch/riscv/configs/rv32_defconfig | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/riscv/
This patch enables more VIRTIO drivers (such as console, rpmsg, 9p,
rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V
Guest.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/configs/defconfig | 11
flush and this will be optimized in future.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_exit.c| 3 +
arch/riscv/kvm
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 81
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
-by: Anup Patel
---
Documentation/virt/kvm/api.txt | 141 +++--
1 file changed, 134 insertions(+), 7 deletions(-)
diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm/api.txt
index 2d067767b617..065c664b0d48 100644
--- a/Documentation/virt/kvm/api.txt
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 25 ++
arch/riscv/kvm/Makefile | 3
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index d75a6c35b6c7..39469f67b241
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so thest functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
From: Atish Patra
Export few symbols used by kvm module. Without this, kvm cannot
be compiled as a module.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/kernel/smp.c | 2 +-
arch/riscv
.
One of the use-case for riscv_isa bitmap is in KVM hypervisor where
we will use it to do following operations:
1. Check whether hypervisor extension is available
2. Find ISA features that need to be virtualized (e.g. floating
point support, vector extension, etc.)
Signed-off-by: Anup Patel
DO NOT UPSTREAM !
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 2 ++
arch/riscv/configs/rv32_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 420a0dbef386..320a7f1da4fc 100644
--- a/arch
ccess to user-space
- Removed irqs_pending_lock and use atomic bitops instead
- Added separate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (16):
KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface
RISC-V: Add bitmap reprensenting ISA features commo
We will be using ONE_REG interface accessing VCPU registers from
user-space hence we add KVM_REG_RISCV for RISC-V VCPU registers.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
include/uapi/linux/kvm.h | 1 +
1 file changed, 1
On Thu, Aug 29, 2019 at 7:27 PM Anup Patel wrote:
>
> Add myself as maintainer for KVM RISC-V as Atish as designated reviewer.
>
> For time being, we use my GitHub repo as KVM RISC-V gitrepo. We will
> update this once we have common KVM RISC-V gitrepo under kernel.org.
>
>
On Thu, Aug 29, 2019 at 7:27 PM Anup Patel wrote:
>
> Document RISC-V specific parts of the KVM API, such as:
> - The interrupt numbers passed to the KVM_INTERRUPT ioctl.
> - The states supported by the KVM_{GET,SET}_MP_STATE ioctls.
> - The registers supported by the KVM_{G
On Thu, Aug 29, 2019 at 7:26 PM Anup Patel wrote:
>
> We will get stage2 page faults whenever Guest/VM access SW emulated
> MMIO device or unmapped Guest RAM.
>
> This patch implements MMIO read/write emulation by extracting MMIO
> details from the trapped load/store instruct
On Tue, Sep 3, 2019 at 2:28 PM Andrew Jones wrote:
>
> On Thu, Aug 29, 2019 at 01:56:18PM +, Anup Patel wrote:
> > int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
> > {
> > - /* TODO: */
> > + u8 data8;
> > +
This patch enables more VIRTIO drivers (such as console, rpmsg, 9p,
rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V
Guest.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/configs/defconfig | 11
Add myself as maintainer for KVM RISC-V as Atish as designated reviewer.
For time being, we use my GitHub repo as KVM RISC-V gitrepo. We will
update this once we have common KVM RISC-V gitrepo under kernel.org.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 81
-by: Anup Patel
---
Documentation/virt/kvm/api.txt | 140 +++--
1 file changed, 133 insertions(+), 7 deletions(-)
diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm/api.txt
index 2d067767b617..80c4ffad8bd7 100644
--- a/Documentation/virt/kvm/api.txt
flush and this will be optimized in future.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_exit.c| 3 +
arch/riscv/kvm
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 25 ++
arch/riscv/kvm/Makefile | 3
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 71 ++
1 file changed, 71 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 700d8158e55b..321062fff65b
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so thest functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
From: Atish Patra
Export few symbols used by kvm module. Without this, kvm cannot
be compiled as a module.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/kernel/smp.c | 2 +-
arch/riscv
.
One of the use-case for riscv_isa bitmap is in KVM hypervisor where
we will use it to do following operations:
1. Check whether hypervisor extension is available
2. Find ISA features that need to be virtualized (e.g. floating
point support, vector extension, etc.)
Signed-off-by: Anup Patel
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58
ded separate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (16):
KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface
RISC-V: Add bitmap reprensenting ISA features common across CPUs
RISC-V: Add hypervisor extension related CSR defines
RISC-V:
We will be using ONE_REG interface accessing VCPU registers from
user-space hence we add KVM_REG_RISCV for RISC-V VCPU registers.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
include/uapi/linux/kvm.h | 1 +
1 file changed, 1
On Tue, Aug 27, 2019 at 5:03 AM Atish Patra wrote:
>
> The SBI v0.2 introduces a base extension which is backward compatible
> with v0.1. Implement all helper functions and minimum required SBI
> calls from v0.2 for now. All other base extension function will be
> added later as per need.
>
>
On Tue, Aug 27, 2019 at 2:09 PM Mike Rapoport wrote:
>
> On Tue, Aug 27, 2019 at 01:53:23PM +0530, Anup Patel wrote:
> > On Tue, Aug 27, 2019 at 1:28 PM Mike Rapoport wrote:
> > >
> > > On Mon, Aug 26, 2019 at 04:32:56PM -0700, Atish Patra wrote:
> > > >
On Tue, Aug 27, 2019 at 1:21 PM Mike Rapoport wrote:
>
> On Mon, Aug 26, 2019 at 04:32:55PM -0700, Atish Patra wrote:
> > As per the new SBI specification, current SBI implementation is
> > defined as legacy and will be removed/replaced in future.
> >
> > Rename existing implementation to reflect
On Tue, Aug 27, 2019 at 1:28 PM Mike Rapoport wrote:
>
> On Mon, Aug 26, 2019 at 04:32:56PM -0700, Atish Patra wrote:
> > The SBI v0.2 introduces a base extension which is backward compatible
> > with v0.1. Implement all helper functions and minimum required SBI
> > calls from v0.2 for now. All
On Tue, Aug 27, 2019 at 5:43 AM Paul Walmsley wrote:
>
> Hello Anup,
>
> On Mon, 19 Aug 2019, Anup Patel wrote:
>
> > Currently, various virtual memory areas of Linux RISC-V are organized
> > in increasing order of their virtual addresses is as follows:
> > 1. Use
On Fri, Aug 23, 2019 at 5:50 PM Alexander Graf wrote:
>
>
>
> On 23.08.19 14:00, Anup Patel wrote:
> > On Fri, Aug 23, 2019 at 5:09 PM Graf (AWS), Alexander
> > wrote:
> >>
> >>
> >>
> >>> Am 23.08.2019 um 13:18 schrieb Anup Pate
On Fri, Aug 23, 2019 at 5:40 PM Paolo Bonzini wrote:
>
> On 23/08/19 13:44, Graf (AWS), Alexander wrote:
> >> Overall, I'm quite happy with the code. It's a very clean implementation
> >> of a KVM target.
>
> Yup, I said the same even for v1 (I prefer recursive implementation of
> page table
On Fri, Aug 23, 2019 at 5:19 PM Alexander Graf wrote:
>
>
>
> On 23.08.19 13:46, Anup Patel wrote:
> > On Fri, Aug 23, 2019 at 5:03 PM Graf (AWS), Alexander
> > wrote:
> >>
> >>
> >>
> >>> Am 23.08.2019 um 13:05 schrieb Anup Pate
On Fri, Aug 23, 2019 at 5:09 PM Graf (AWS), Alexander wrote:
>
>
>
> > Am 23.08.2019 um 13:18 schrieb Anup Patel :
> >
> >> On Fri, Aug 23, 2019 at 1:34 PM Alexander Graf wrote:
> >>
> >>> On 22.08.19 10:46, Anup Patel wrote:
> >>> F
On Fri, Aug 23, 2019 at 5:03 PM Graf (AWS), Alexander wrote:
>
>
>
> > Am 23.08.2019 um 13:05 schrieb Anup Patel :
> >
> >> On Fri, Aug 23, 2019 at 1:23 PM Alexander Graf wrote:
> >>
> >>> On 22.08.19 10:46, Anup Patel wrote:
> &g
On Fri, Aug 23, 2019 at 1:39 PM Alexander Graf wrote:
>
> On 22.08.19 10:42, Anup Patel wrote:
> > This series adds initial KVM RISC-V support. Currently, we are able to boot
> > RISC-V 64bit Linux Guests with multiple VCPUs.
> >
> > Few key aspects of KVM RISC-V a
On Thu, Aug 22, 2019 at 7:39 PM Alexander Graf wrote:
>
>
>
> On 22.08.19 15:58, Anup Patel wrote:
> > On Thu, Aug 22, 2019 at 6:57 PM Alexander Graf wrote:
> >>
> >>
> >>
> >> On 22.08.19 14:38, Anup Patel wrote:
>
On Thu, Aug 22, 2019 at 7:42 PM Alexander Graf wrote:
>
>
>
> On 22.08.19 16:00, Anup Patel wrote:
> > On Thu, Aug 22, 2019 at 5:31 PM Alexander Graf wrote:
> >>
> >> On 22.08.19 10:44, Anup Patel wrote:
> >>> For KVM RISC-V, we use KVM_GET_ONE
On Fri, Aug 23, 2019 at 1:34 PM Alexander Graf wrote:
>
> On 22.08.19 10:46, Anup Patel wrote:
> > From: Atish Patra
> >
> > The KVM host kernel running in HS-mode needs to handle SBI calls coming
> > from guest kernel running in VS-mode.
> >
> > This
On Fri, Aug 23, 2019 at 1:23 PM Alexander Graf wrote:
>
> On 22.08.19 10:46, Anup Patel wrote:
> > From: Atish Patra
> >
> > The RISC-V hypervisor specification doesn't have any virtual timer
> > feature.
> >
> > Due to this, the guest VCPU timer will
On Thu, Aug 22, 2019 at 5:31 PM Alexander Graf wrote:
>
> On 22.08.19 10:44, Anup Patel wrote:
> > For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
> > VCPU config and registers from user-space.
> >
> > We have three types of VCPU registers:
On Thu, Aug 22, 2019 at 5:31 PM Alexander Graf wrote:
>
> On 22.08.19 10:44, Anup Patel wrote:
> > For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
> > VCPU config and registers from user-space.
> >
> > We have three types of VCPU registers:
On Thu, Aug 22, 2019 at 6:57 PM Alexander Graf wrote:
>
>
>
> On 22.08.19 14:38, Anup Patel wrote:
> > On Thu, Aug 22, 2019 at 5:58 PM Alexander Graf wrote:
> >>
> >> On 22.08.19 10:45, Anup Patel wrote:
> >>> This patch implements all required
On Thu, Aug 22, 2019 at 6:55 PM Alexander Graf wrote:
>
>
>
> On 22.08.19 14:33, Anup Patel wrote:
> > On Thu, Aug 22, 2019 at 5:44 PM Alexander Graf wrote:
> >>
> >> On 22.08.19 10:44, Anup Patel wrote:
> >>> We will get stage2 page faults whenev
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