This patch enables more VIRTIO drivers (such as console, rpmsg, 9p,
rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V
Guest.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 23 ++-
arch/riscv/configs/rv32_defconfig | 13 +
2
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 10 +++
arch
Add myself as maintainer for KVM RISC-V as Atish as designated reviewer.
For time being, we use my GitHub repo as KVM RISC-V gitrepo. We will
update this once we have common KVM RISC-V gitrepo under kernel.org.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
MAINTAINERS | 10
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
---
arch
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 7
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu.c | 30 -
arch/riscv/kvm/vcpu_switch.S
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 21 +
arch/riscv/kvm/Makefile | 3 +-
arch/riscv/kvm/main.c | 4 +
arch/riscv/kvm/tlb.S
.
Signed-off-by: Anup Patel
---
arch/riscv/kvm/vcpu_exit.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index efc06198c259..f4ddf357ded8 100644
--- a/arch/riscv/kvm/vcpu_exit.c
+++ b/arch/riscv
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2 +
arch/riscv/Makefile | 2 +
arch/riscv/include/asm/kvm_host.h | 79
From: Atish Patra
Export few symbols used by kvm module. Without this, kvm cannot
be compiled as a module.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/riscv/kernel/smp.c | 2 +-
arch/riscv/kernel/time.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 11
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so thest functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 68
We will be using ONE_REG interface accessing VCPU registers from
user-space hence we add KVM_REG_RISCV for RISC-V VCPU registers.
Signed-off-by: Anup Patel
---
include/uapi/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
ated ONE_REG interface for CSR access to user-space
- Removed irqs_pending_lock and use atomic bitops instead
- Added separate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (14):
KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface
RISC-V: Add hy
On Tue, Jul 30, 2019 at 7:38 PM Paolo Bonzini wrote:
>
> On 30/07/19 15:35, Anup Patel wrote:
> > On Tue, Jul 30, 2019 at 6:48 PM Paolo Bonzini wrote:
> >>
> >> On 30/07/19 14:45, Anup Patel wrote:
> >>> Here's some text from RISC-V spec regarding SIP CS
On Tue, Jul 30, 2019 at 4:50 PM Paolo Bonzini wrote:
>
> On 29/07/19 13:57, Anup Patel wrote:
> > +static ulong get_insn(struct kvm_vcpu *vcpu)
> > +{
> > + ulong __sepc = vcpu->arch.guest_context.sepc;
> > + ulong __hstatus, __sstatus, __vsstatu
On Wed, Jul 31, 2019 at 12:28 PM Paolo Bonzini wrote:
>
> On 31/07/19 03:55, Atish Patra wrote:
> > On Tue, 2019-07-30 at 13:26 +0200, Paolo Bonzini wrote:
> >> On 29/07/19 13:57, Anup Patel wrote:
> >>> + if (delta_ns > VCPU_TIMER_PROGRAM_THRESHOLD_NS) {
On Tue, Jul 30, 2019 at 5:03 PM Paolo Bonzini wrote:
>
> On 30/07/19 07:26, Anup Patel wrote:
> > Here's a brief TODO list which we want to immediately work upon after this
> > series:
> > 1. Handle trap from unpriv access in SBI v0.1 emulation
> > 2. In-kernel
On Tue, Jul 30, 2019 at 6:48 PM Paolo Bonzini wrote:
>
> On 30/07/19 14:45, Anup Patel wrote:
> > Here's some text from RISC-V spec regarding SIP CSR:
> > "software interrupt-pending (SSIP) bit in the sip register. A pending
> > supervisor-level software interrup
On Tue, Jul 30, 2019 at 3:04 PM Paolo Bonzini wrote:
>
> On 29/07/19 13:57, Anup Patel wrote:
> > void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
> > {
> > - /* TODO: */
> > + struct kvm_vcpu_csr *csr = >arch.guest_csr;
> > +
> &
On Tue, Jul 30, 2019 at 5:42 PM Paolo Bonzini wrote:
>
> On 30/07/19 14:00, Anup Patel wrote:
> > On Tue, Jul 30, 2019 at 4:47 PM Paolo Bonzini wrote:
> >>
> >> First, something that is not clear to me: how do you deal with a guest
> >> writing 1 to VSIP
On Tue, Jul 30, 2019 at 5:40 PM Paolo Bonzini wrote:
>
> On 30/07/19 14:08, Anup Patel wrote:
> >> Still, I would prefer all the VS CSRs to be accessible via the get/set
> >> reg ioctls.
> > We had implemented VS CSRs access to user-space but then we
> > r
On Tue, Jul 30, 2019 at 2:30 PM Paolo Bonzini wrote:
>
> On 29/07/19 13:57, Anup Patel wrote:
> > This patch implements all required functions for programming
> > the stage2 page table for each Guest/VM.
> >
> > At high-level, the flow of stage2 related functions is
On Tue, Jul 30, 2019 at 3:05 PM Paolo Bonzini wrote:
>
> On 30/07/19 10:43, Paolo Bonzini wrote:
> > On 29/07/19 13:56, Anup Patel wrote:
> >> The PC register represents program counter whereas the MODE
> >> register represent VCPU privilege mode (i.e. S/U-mode)
gt;
> mask = xchg_acquire(>arch.irqs_pending_mask, 0);
> val = READ_ONCE(vcpu->arch.irqs_pending) & mask;
>
> vcpu->arch.guest_csr.vsip &= ~mask;
> vcpu->arch.guest_csr.vsip |= val;
> csr_wri
On Tue, Jul 30, 2019 at 3:46 PM Paolo Bonzini wrote:
>
> On 30/07/19 10:48, Paolo Bonzini wrote:
> > On 29/07/19 13:56, Anup Patel wrote:
> >> +cntx->hstatus |= HSTATUS_SP2V;
> >> +cntx->hstatus |= HSTATUS_SP2P;
> > IIUC, cntx->hstatus's
On Tue, Jul 30, 2019 at 2:53 PM Paolo Bonzini wrote:
>
> On 29/07/19 13:56, Anup Patel wrote:
> > + case KVM_CAP_DEVICE_CTRL:
> > + case KVM_CAP_USER_MEMORY:
> > + case KVM_CAP_SYNC_MMU:
>
> Technically KVM_CAP_SYNC_MMU should only be added after you
On Tue, Jul 30, 2019 at 2:55 PM Paolo Bonzini wrote:
>
> On 29/07/19 13:56, Anup Patel wrote:
> > +void kvm_riscv_halt_guest(struct kvm *kvm)
> > +{
> > + int i;
> > + struct kvm_vcpu *vcpu;
> > +
> > + kvm_for_each_vcpu(i, vcpu, kvm)
On Tue, Jul 30, 2019 at 12:23 PM Andreas Schwab wrote:
>
> ERROR: "riscv_cs_get_mult_shift" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "riscv_isa" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "smp_send_reschedule" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "riscv_timebase"
On Tue, Jul 30, 2019 at 12:23 PM Andreas Schwab wrote:
>
> ERROR: "riscv_cs_get_mult_shift" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "riscv_isa" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "smp_send_reschedule" [arch/riscv/kvm/kvm.ko] undefined!
> ERROR: "riscv_timebase"
On Tue, Jul 30, 2019 at 3:17 AM Paolo Bonzini wrote:
>
> On 29/07/19 13:56, Anup Patel wrote:
> > This series adds initial KVM RISC-V support. Currently, we are able to boot
> > RISC-V 64bit Linux Guests with multiple VCPUs.
> >
> > Few key aspects of KVM RISC-V a
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 11
This patch enables more VIRTIO drivers (such as console, rpmsg, 9p,
rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V
Guest.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 23 ++-
arch/riscv/configs/rv32_defconfig | 13 +
2
flush and this will be optimized in future.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_exit.c| 3 +
arch/riscv/kvm/vcpu_sbi.c | 118
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 7
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 75 +
arch/riscv/kvm/vcpu_switch.S | 174 ++
4
such as FP, CSRs, etc
for KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 24
arch/riscv/kvm/vcpu.c | 177 +-
2 files changed, 199 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu.c | 33 -
arch/riscv/kvm/vcpu_switch.S
.
Signed-off-by: Anup Patel
---
arch/riscv/kvm/vcpu_exit.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 4dafefa59338..2d09640c98b2 100644
--- a/arch/riscv/kvm/vcpu_exit.c
+++ b/arch/riscv
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 13 +++
arch/riscv/include/uapi/asm/kvm.h | 3 +
arch/riscv/kvm/vcpu.c | 174 +++---
3 files changed, 177 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h
b/arch
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_PGTBL
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 21 +
arch/riscv/kvm/Makefile | 3 +-
arch/riscv/kvm/main.c | 4 +
arch/riscv/kvm/tlb.S
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2 +
arch/riscv/Makefile | 2 +
arch/riscv/include/asm/kvm_host.h | 82
We will be using ONE_REG interface accessing VCPU registers from
user-space hence we add KVM_REG_RISCV for RISC-V VCPU registers.
Signed-off-by: Anup Patel
---
include/uapi/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index
h RISC-V Guest Linux with initrd:
$ ./apps/lkvm-static run -m 128 -c2 --console serial \
-p "console=ttyS0 earlycon=uart8250,mmio,0x3f8" -k ./apps/Image \
-i ./apps/rootfs.img --debug
Anup Patel (13):
KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface
RISC-V: Add hypervisor extensio
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so thest functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 70
On Sat, Jul 27, 2019 at 1:46 PM Paul Walmsley wrote:
>
> On Sat, 27 Jul 2019, Anup Patel wrote:
>
> > If your only objection is uppercase letter not agreeing with YMAL schema
> > then why not fix the YMAL schema to have regex for RISC-V ISA string?
>
On Sat, Jul 27, 2019 at 1:23 PM Paul Walmsley wrote:
>
> On Sat, 27 Jul 2019, Anup Patel wrote:
>
> > > -Original Message-
> > > From: Paul Walmsley
> > > Sent: Saturday, July 27, 2019 5:00 AM
> > >
> > > On Fri, 26 Jul 2019, Ati
> -Original Message-
> From: Paul Walmsley
> Sent: Saturday, July 27, 2019 5:00 AM
> To: Atish Patra
> Cc: linux-kernel@vger.kernel.org; Alan Kao ;
> Albert Ou ; Allison Randal ;
> Anup Patel ; Daniel Lezcano
> ; Greg Kroah-Hartman
> ; Johan Hovold ; linux-
On Tue, Jun 25, 2019 at 2:53 AM Paul Walmsley wrote:
>
> On Mon, 24 Jun 2019, Yash Shah wrote:
>
> > As per the General convention, define only device DT node in SOC DTSi
> > file with status = "disabled" and enable device in Board DTS file with
> > status = &
On Fri, Jun 7, 2019 at 11:31 AM Anup Patel wrote:
>
> This patchset implements two-stagged initial page table setup using fixmap
> to avoid mapping non-existent RAM and also reduce high_memory consumed by
> initial page tables.
>
> The patchset is based on Linux-5.2-rc3 an
00.dts
> b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> index 4da8870..d783bf2 100644
> --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -63,3 +63,12 @@
> disable-wp;
> };
> };
> +
> + {
> + status = "okay";
> + phy-mode = "gmii";
> + phy-handle = <>;
> + phy1: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
> --
> 1.9.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Jun 21, 2019 at 11:40 AM Yash Shah wrote:
>
> DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git
On Tue, Jun 18, 2019 at 8:56 AM Paul Walmsley wrote:
>
> On Mon, 17 Jun 2019, Alistair Francis wrote:
>
> > > The legacy M-mode U-boot handles the phy reset already, and I’ve been
> > > able to load upstream S-mode uboot as a payload via TFTP, and then
> > > load and boot a 4.19 kernel.
> > >
> >
kernel
mappings where we protect kernel text and rodata using PTE permissions.
Suggested-by: Mike Rapoport
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/asm/pgtable-64.h | 5 +
arch/riscv/include/asm/pgtable.h| 8 +
arch/riscv/kernel/head.S
Rapoport
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/mm/init.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 8bf6f9c2d48c..1879501bd156 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv
ded PATCH4 to remove redundant trampoline page table
- Added PATCH5 to fix memory reservation in setup_bootmem()
Anup Patel (2):
RISC-V: Fix memory reservation in setup_bootmem()
RISC-V: Setup initial page tables in two stages
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/a
On Tue, Jun 4, 2019 at 1:47 AM Troy Benjegerdes
wrote:
>
>
>
> > On Jun 3, 2019, at 4:49 AM, Loys Ollivier wrote:
> >
> > On Wed 29 May 2019 at 12:25, Troy Benjegerdes
> > wrote:
> >
> >>> On May 29, 2019, at 5:04 AM, Loys Ollivier wrote:
> >>>
> >>> On Wed 29 May 2019 at 00:50, Atish Patra
Hi All,
It's a great pleasure to inform everyone that we have RISC-V
hypervisor extension available for QEMU and along with it we
also have Xvisor (a baremetal type-1 hypervisor) working on
QEMU with RISC-V hypervisor extension. Currently, we are able
to boot two Linux RV64 Guests on Xvisor RV64.
> -Original Message-
> From: Karsten Merker
> Sent: Tuesday, May 28, 2019 1:53 PM
> To: Anup Patel
> Cc: Troy Benjegerdes ; Karsten Merker
> ; Albert Ou ; Jonathan
> Corbet ; Ard Biesheuvel ;
> linux-kernel@vger.kernel.org List ; Zong Li
> ; Atish Patra ; Pa
> -Original Message-
> From: Troy Benjegerdes
> Sent: Tuesday, May 28, 2019 5:11 AM
> To: Karsten Merker
> Cc: Ard Biesheuvel ; Albert Ou
> ; Jonathan Corbet ; Anup Patel
> ; Zong Li ; Atish Patra
> ; Nick Kossifidis ; Palmer Dabbelt
> ; paul.walms
On Mon, May 20, 2019 at 5:13 PM Christoph Hellwig wrote:
>
> > void __init parse_dtb(unsigned int hartid, void *dtb)
> > {
> > - if (early_init_dt_scan(__va(dtb)))
> > + dtb = (void *)fix_to_virt(FIX_FDT) + ((uintptr_t)dtb & ~PAGE_MASK);
> > + if (early_init_dt_scan(dtb))
>
> FYI,
On Thu, May 2, 2019 at 10:32 AM Anup Patel wrote:
>
> This patchset implements two-stagged initial page table setup using fixmap
> to avoid mapping non-existent RAM and also reduce high_memory consumed by
> initial page tables.
>
> The patchset is based on Linux-5.1-rc7 an
On Wed, May 15, 2019 at 12:00 PM Anup Patel wrote:
>
> This patch enables NO_HZ_IDLE (idle dynamic ticks) and HIGH_RES_TIMERS
> (hrtimers) in RV32 and RV64 defconfigs.
>
> Both of the above options are enabled by default for architectures
> such as x86, ARM, and ARM64.
>
>
is idle whereas hrtimers is a much improved timer
subsystem compared to the old "timer wheel" based system.
This patch is tested on SiFive Unleashed board and QEMU Virt machine.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 2 ++
arch/riscv/configs/rv32_defconfig | 2 +
Rapoport
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/mm/init.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index bc7b77e34d09..ab175b655933 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv
kernel
mappings where we protect kernel text and rodata using PTE permissions.
Suggested-by: Mike Rapoport
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/asm/pgtable-64.h | 5 +
arch/riscv/include/asm/pgtable.h| 7 +
arch/riscv/kernel/head.S
fix memory reservation in setup_bootmem()
Anup Patel (2):
RISC-V: Fix memory reservation in setup_bootmem()
RISC-V: Setup initial page tables in two stages
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/asm/pgtable-64.h | 5 +
arch/riscv/include/asm/pgtable.h| 7 +
arch/ri
On Wed, May 1, 2019 at 10:30 PM Mark Rutland wrote:
>
> On Mon, Apr 29, 2019 at 10:42:40PM -0700, Atish Patra wrote:
> > On 4/29/19 4:40 PM, Palmer Dabbelt wrote:
> > > On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.pa...@wdc.com wrote:
> > > > Currently, last stage boot loaders such as U-Boot
On Wed, May 1, 2019 at 10:14 PM Karsten Merker wrote:
>
> On Mon, Apr 29, 2019 at 10:42:40PM -0700, Atish Patra wrote:
> > On 4/29/19 4:40 PM, Palmer Dabbelt wrote:
> > > On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.pa...@wdc.com wrote:
> > > > Currently, last stage boot loaders such as U-Boot
On Fri, Apr 26, 2019 at 11:51 AM Christoph Hellwig wrote:
>
> On Thu, Apr 25, 2019 at 09:41:21PM -0700, Atish Patra wrote:
> > Do we even need HVC_SBI console to be enabled by default? Disabling
> > CONFIG_HVC_RISCV_SBI seems to be fine while running in QEMU.
> >
> > If we don't need it, I
On Fri, Apr 26, 2019 at 10:11 AM Atish Patra wrote:
>
> On 4/25/19 6:35 AM, Anup Patel wrote:
> > The Linux kernel will auto-disables all boot consoles whenever it
> > gets a preferred real console.
> >
> > Currently on RISC-V systems, if we have a real console whic
V SBI console driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
drivers/tty/hvc/hvc_riscv_sbi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 75155bde2b88..31f53fa77e4a 100644
--- a/drivers/tty/hvc/hvc
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 21 +
arch/riscv
which beautifies asm/csr.h by using tabs to
align macro values
Changes since v1:
- Squash PATCH2 into cpatch3
- Added new PATCH2 to add interrupt related SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE d
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
On Thu, Apr 25, 2019 at 1:31 PM Christoph Hellwig wrote:
>
> On Thu, Apr 25, 2019 at 12:46:52PM +0530, Anup Patel wrote:
> > On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig
> > wrote:
> > >
> > > > +#ifdef CONFIG_64BIT
> > > > +#define SCAU
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 21 +
arch/riscv
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
nce v1:
- Squash PATCH2 into cpatch3
- Added new PATCH2 to add interrupt related SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
RISC-V: Access CSRs using CSR numbers
arch/riscv/i
On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig wrote:
>
> > +#ifdef CONFIG_64BIT
> > +#define SCAUSE_IRQ_FLAG _AC(0x8000, UL)
> > +#else
> > +#define SCAUSE_IRQ_FLAG _AC(0x8000, UL)
> > +#endif
>
> Please keep the existing defintion that doesn't need
elated SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
RISC-V: Access CSRs using CSR numbers
arch/riscv/include/asm/csr.h | 127 +--
arch/riscv/i
This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
defines to asm/csr.h. We also use these defines in kernel/irq.c and
express SIE/SIP flags in-terms of SCAUSE interrupt causes.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 25 +
arch/riscv
.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 32 ++--
arch/riscv/include/asm/irqflags.h| 10 -
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S| 22
The spacing between macro name and value is not consistent in
asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
macro values instead of spaces.
Signed-off-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
arch/riscv/include/asm/csr.h | 76 ++--
1
On Wed, Apr 24, 2019 at 8:31 PM Christoph Hellwig wrote:
>
> On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote:
> > We need these defines for programming HIDELEG CSR in KVM kernel module
> > so it will be used at multiple places.
> >
> > >
> &g
> -Original Message-
> > From: Anup Patel
> > Sent: Thursday, April 25, 2019 03:04
> > To: Palmer Dabbelt
> > Cc: Anup Patel ; Albert Ou ;
> > Gary Guo ; Atish Patra ; Christoph
> > Hellwig ; Paul Walmsley ;
> > Mike Rapoport ; linux-ri...@lis
> -Original Message-
> From: Gary Guo
> Sent: Thursday, April 25, 2019 8:19 AM
> To: Anup Patel ; Palmer Dabbelt
>
> Cc: Anup Patel ; Albert Ou
> ; Atish Patra ; Christoph
> Hellwig ; Paul Walmsley ;
> Mike Rapoport ; linux-ri...@lists.infradead.org; linu
uld not be a
reason to defer critical changes as long as changes are tested on existing HW.
Linux kernel is all about "organic development". We start with a reasonable
implementation of any thing and perfect it incrementally over time. That's how
we get a solid implementation.
Regards,
A
)
> /* Number of entries in the page table */
> -#define PTRS_PER_PTE(PAGE_SIZE / sizeof(pte_t))
> +#ifdef __PAGETABLE_PMD_FOLDED
> +#define PTRS_PER_PTE (1 << (PGDIR_SHIFT - PAGE_SHIFT))
> +#else
> +#define PTRS_PER_PTE (1 << (PMD_SHIFT - PAGE_SHIFT))
> +#endif
>
> /* Number of PGD entries that a user-mode program can use */
> #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
> --
> 1.9.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
LDED
> +#define PTRS_PER_PTE (1 << (PGDIR_SHIFT - PAGE_SHIFT))
> +#else
> +#define PTRS_PER_PTE (1 << (PMD_SHIFT - PAGE_SHIFT))
> +#endif
>
> /* Number of PGD entries that a user-mode program can use */
> #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
> --
> 1.9.1
>
Apart from above, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig wrote:
>
> On Mon, Apr 15, 2019 at 09:37:23AM +, Anup Patel wrote:
> > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
> > defines to asm/csr.h. We also use these defines in kernel/irq.c and
> &g
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