[PATCH v5 6/6] RISC-V: Free-up initrd in free_initrd_mem()

We should free-up initrd memory in free_initrd_mem() instead of doing nothing. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9cd583b6d1cd..ed8dd28ca98c

[PATCH v5 3/6] RISC-V: Move setup_bootmem() to mm/init.c

The setup_bootmem() mainly populates memblocks and does early memory reservations. The right location for this function is mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/setup.c

[PATCH v5 1/6] RISC-V: Move free_initrd_mem() to kernel/setup.c

We move free_initrd_mem() to kernel/setup.c so that all initrd related functions are in one place. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/setup.c | 4 arch/riscv/mm/init.c | 7 --- 2 files changed, 4 insertions

[PATCH v5 0/6] Fixmap support and MM cleanups

- Use more characters per line in commets of PATCH5 - Added PATCH6 to implement keepinitrd kernel parameter Anup Patel (6): RISC-V: Move free_initrd_mem() to kernel/setup.c RISC-V: Setup init_mm before parse_early_param() RISC-V: Move setup_bootmem() to mm/init.c RISC-V: Move setup_vm() to

RE: [PATCH v4 6/6] RISC-V: Free-up initrd in free_initrd_mem()

> -Original Message- > From: Mike Rapoport [mailto:r...@linux.ibm.com] > Sent: Wednesday, February 13, 2019 1:09 PM > To: Christoph Hellwig > Cc: Anup Patel ; Palmer Dabbelt > ; Albert Ou ; Atish Patra > ; Paul Walmsley ; linux- > ri...@lists.infradead.org; linu

Re: [v4 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init

ors now. > > Do not proceed if hartid or cpuid is invalid. Take this opprtunity to s/opprtunity/opportunity Otherwise, looks good to me. Reviewed-by: Anup Patel Regards, Anup

[PATCH v4 5/6] RISC-V: Implement compile-time fixed mappings

This patch implements compile-time virtual to physical mappings. These compile-time fixed mappings can be used by earlycon, ACPI, and early ioremap for creating fixed mappings when FIX_EARLYCON_MEM=y. To start with, we have enabled compile-time fixed mappings for earlycon. Signed-off-by: Anup

[PATCH v4 2/6] RISC-V: Setup init_mm before parse_early_param()

We should setup init_mm before doing parse_early_param() in setup_arch() to be consistent with setup_arch() of other architectures such as x86, ARM, and ARM64. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/setup.c | 9 - 1

[PATCH v4 4/6] RISC-V: Move setup_vm() to mm/init.c

The setup_vm() is responsible for setting up initial page table hence should be placed in mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/setup.c | 49 --- arch/riscv/mm/init.c | 49

[PATCH v4 3/6] RISC-V: Move setup_bootmem() to mm/init.c

The setup_bootmem() mainly populates memblocks and does early memory reservations. The right location for this function is mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/setup.c

[PATCH v4 6/6] RISC-V: Free-up initrd in free_initrd_mem()

We should free-up initrd memory in free_initrd_mem() instead of doing nothing. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9cd583b6d1cd..c22b873de856

[PATCH v4 1/6] RISC-V: Move free_initrd_mem() to kernel/setup.c

We move free_initrd_mem() to kernel/setup.c so that all initrd related functions are in one place. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/setup.c | 4 arch/riscv/mm/init.c | 7 --- 2 files changed, 4 insertions

[PATCH v4 0/6] Fixmap support and MM cleanups

implement keepinitrd kernel parameter Anup Patel (6): RISC-V: Move free_initrd_mem() to kernel/setup.c RISC-V: Setup init_mm before parse_early_param() RISC-V: Move setup_bootmem() to mm/init.c RISC-V: Move setup_vm() to mm/init.c RISC-V: Implement compile-time fixed mappings RISC-V: Free

RE: [PATCH v2 6/6] RISC-V: Implement keepinitrd kernel parameter

> -Original Message- > From: Christoph Hellwig [mailto:h...@infradead.org] > Sent: Wednesday, February 13, 2019 11:25 AM > To: Anup Patel > Cc: Christoph Hellwig ; Anup Patel > ; Palmer Dabbelt ; linux- > ker...@vger.kernel.org; Atish Patra ; Albert Ou > ; Pa

RE: [PATCH v2 6/6] RISC-V: Implement keepinitrd kernel parameter

> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Christoph Hellwig > Sent: Wednesday, February 13, 2019 12:15 AM > To: Anup Patel > Cc: Christoph Hellwig ; Palmer Dabbelt > ; Anup

[PATCH v3 6/6] RISC-V: Implement keepinitrd kernel parameter

hitectures and it is documented at: Documentation/admin-guide/kernel-parameters.txt Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9cd583b6d1cd..46e547dd8

[PATCH v3 2/6] RISC-V: Setup init_mm before parse_early_param()

We should setup init_mm before doing parse_early_param() in setup_arch() to be consistent with setup_arch() of other architectures such as x86, ARM, and ARM64. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/setup.c | 9 - 1 file changed, 4 insertions

[PATCH v3 5/6] RISC-V: Implement compile-time fixed mappings

This patch implements compile-time virtual to physical mappings. These compile-time fixed mappings can be used by earlycon, ACPI, and early ioremap for creating fixed mappings when FIX_EARLYCON_MEM=y. To start with, we have enabled compile-time fixed mappings for earlycon. Signed-off-by: Anup

[PATCH v3 4/6] RISC-V: Move setup_vm() to mm/init.c

The setup_vm() is responsible for setting up initial page table hence should be placed in mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/setup.c | 49 --- arch/riscv/mm/init.c | 49

[PATCH v3 3/6] RISC-V: Move setup_bootmem() to mm/init.c

The setup_bootmem() mainly populates memblocks and does early memory reservations. The right location for this function is mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/setup.c| 48

[PATCH v3 1/6] RISC-V: Move free_initrd_mem() to kernel/setup.c

We move free_initrd_mem() to kernel/setup.c so that all initrd related functions are in one place. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/setup.c | 4 arch/riscv/mm/init.c | 7 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff

[PATCH v3 0/6] Fixmap support and MM cleanups

From: Anup Patel This patchset does: 1. Moves MM related code from kernel/setup.c to mm/init.c 2. Implements compile-time fixed mappings Using fixed mappings available, we can now get earlyprints even without SBI calls. For example, we can use kernel parameter "earlycon=uart8250,mmio,0x100

Re: [PATCH v2 6/6] RISC-V: Implement keepinitrd kernel parameter

On Tue, Feb 12, 2019 at 4:07 PM Andreas Schwab wrote: > > On Feb 12 2019, Anup Patel wrote: > > > So in case of initrd we might not want to free-up the RAM but > > we can certainly free-up in case of initramfs. > > But the default should be keepinitrd=0, shoudn't it?

[PATCH v6 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context

uot;nr_contexts" and "nr_mapped" to "nr_handlers" in plic_init(). Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sif

[PATCH v6 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers

[PATCH v6 2/4] irqchip: sifive-plic: Add warning in plic_init() if handler already present

updated interrupts-extended DT property. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index c23a293a2aae..da09f46fad64

[PATCH v6 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

693 77410 Rescheduling interrupts IPI1: 0 2 3 16 Function call interrupts Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 45 ++- 1 file changed, 39 insertions(+)

[PATCH v6 0/4] IRQ affinity support in PLIC driver

n PATCH1 - Retained comment about need for locking in PATCH1 - Split PATCH2 into two patches - Split PATCH3 into two patches - Minor fix in commit description of PATCH4 Changes since v1: - Removed few whitspace changes from PATCH1 - Keep use of DEFINE_PER_CPU() as it is Anup Patel (4): irqch

Re: [PATCH v5 2/5] irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle()

On Tue, Feb 12, 2019 at 12:39 PM Christoph Hellwig wrote: > > On Sat, Jan 19, 2019 at 11:26:22AM +0530, Anup Patel wrote: > > The plic_toggle() uses raw_spin_lock() and plic_irq_toggle has a > > for loop so both these functions are not suitable for being inline > >

Re: [PATCH v2 6/6] RISC-V: Implement keepinitrd kernel parameter

On Tue, Feb 12, 2019 at 12:38 PM Christoph Hellwig wrote: > > On Sat, Jan 19, 2019 at 01:28:59PM +, Anup Patel wrote: > > This patch implements keepinitrd kernel parameter. By default, > > keepinitrd=1 but users can pass "keepinitrd=0" to free-up &g

Re: [PATCH v2 0/6] Fixmap support and MM cleanups

Hi All, Any comments on this series ?? Regards, Anup

[PATCH v2 6/6] RISC-V: Implement keepinitrd kernel parameter

documented at: Documentation/admin-guide/kernel-parameters.txt Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9cd583b6d1cd..46e547dd8245 100644

[PATCH v2 5/6] RISC-V: Implement compile-time fixed mappings

This patch implements compile-time virtual to physical mappings. These compile-time fixed mappings can be used by earlycon, ACPI, and early ioremap for creating fixed mappings when FIX_EARLYCON_MEM=y. To start with, we have enabled compile-time fixed mappings for earlycon. Signed-off-by: Anup

[PATCH v2 4/6] RISC-V: Move setup_vm() to mm/init.c

The setup_vm() is responsible for setting up initial page table hence should be placed in mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/setup.c | 49 --- arch/riscv/mm/init.c | 49

[PATCH v2 3/6] RISC-V: Move setup_bootmem() to mm/init.c

The setup_bootmem() mainly populates memblocks and does early memory reservations. The right location for this function is mm/init.c. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/setup.c| 48

[PATCH v2 1/6] RISC-V: Move free_initrd_mem() to kernel/setup.c

We move free_initrd_mem() to kernel/setup.c so that all initrd related functions are in one place. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/setup.c | 4 arch/riscv/mm/init.c | 7 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff

[PATCH v2 0/6] Fixmap support and MM cleanups

- Removed #ifndef __ASSEMBLY__ from PATCH5 - Use more characters per line in commets of PATCH5 - Added PATCH6 to implement keepinitrd kernel parameter Anup Patel (6): RISC-V: Move free_initrd_mem() to kernel/setup.c RISC-V: Setup init_mm before parse_early_param() RISC-V: Move setup_bootmem() to

[PATCH v2 2/6] RISC-V: Setup init_mm before parse_early_param()

We should setup init_mm before doing parse_early_param() in setup_arch() to be consistent with setup_arch() of other architectures such as x86, ARM, and ARM64. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git

Re: [PATCH 5/5] RISC-V: Implement compile-time fixed mappings

On Tue, Jan 15, 2019 at 7:17 PM Christoph Hellwig wrote: > > On Mon, Jan 07, 2019 at 09:40:47PM +0530, Anup Patel wrote: > > From: Anup Patel > > > > This patch implements compile-time virtual to physical > > mappings. These compile-time fixed mappings can

Re: [PATCH 5/5] RISC-V: Implement compile-time fixed mappings

On Tue, Jan 15, 2019 at 7:17 PM Christoph Hellwig wrote: > > On Mon, Jan 07, 2019 at 09:40:47PM +0530, Anup Patel wrote: > > From: Anup Patel > > > > This patch implements compile-time virtual to physical > > mappings. These compile-time fixed mappings can

Re: [PATCH 3/5] RISC-V: Move setup_bootmem() to mm/init.c

On Tue, Jan 15, 2019 at 7:14 PM Christoph Hellwig wrote: > > On Mon, Jan 07, 2019 at 09:40:45PM +0530, Anup Patel wrote: > > From: Anup Patel > > > > The setup_bootmem() mainly populates memblocks and does > > early memory reservations. The right location for

Re: [PATCH 2/5] RISC-V: Setup init_mm before parse_early_param()

On Tue, Jan 15, 2019 at 7:14 PM Christoph Hellwig wrote: > > On Mon, Jan 07, 2019 at 09:40:44PM +0530, Anup Patel wrote: > > From: Anup Patel > > > > We should setup init_mm before doing parse_early_param() > > in setup_arch() to be consistent with setup_arc

Re: [PATCH 1/5] RISC-V: Move free_initrd_mem() to kernel/setup.c

On Tue, Jan 15, 2019 at 7:13 PM Christoph Hellwig wrote: > > On Mon, Jan 07, 2019 at 09:40:43PM +0530, Anup Patel wrote: > > From: Anup Patel > > > > We move free_initrd_mem() to kernel/setup.c so that all initrd > > related functions are in one place. >

[PATCH v5 4/5] irqchip: sifive-plic: Differentiate between PLIC handler and context

uot;nr_contexts" and "nr_mapped" to "nr_handlers" in plic_init(). Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqc

[PATCH v5 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

693 77410 Rescheduling interrupts IPI1: 0 2 3 16 Function call interrupts Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 44 ++- 1 file changed, 38 insertions(+)

[PATCH v5 3/5] irqchip: sifive-plic: Add warning in plic_init() if handler already present

updated interrupts-extended DT property. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 01ffbcae..b9a0bcefe426

[PATCH v5 2/5] irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle()

The plic_toggle() uses raw_spin_lock() and plic_irq_toggle has a for loop so both these functions are not suitable for being inline hence this patch removes the inline keyword. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 6 +++--- 1 file changed, 3 insertions(+), 3

[PATCH v5 1/5] irqchip: sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 47

[PATCH v5 0/5] IRQ affinity support in PLIC driver

CH2 into two patches - Split PATCH3 into two patches - Minor fix in commit description of PATCH4 Changes since v1: - Removed few whitspace changes from PATCH1 - Keep use of DEFINE_PER_CPU() as it is Anup Patel (5): irqchip: sifive-plic: Pre-compute context hart base and enable base irqchip

Re: [PATCH v4 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

On Tue, Jan 15, 2019 at 9:27 PM Christoph Hellwig wrote: > > > + if (!force) > > + cpu = cpumask_any_and(mask_val, cpu_online_mask); > > + else > > + cpu = cpumask_first(mask_val); > > Any reason for the inverted test? Okay, I will not use inverted test here. > >

Re: [PATCH v4 4/5] irqchip: sifive-plic: Differentiate between PLIC handler and context

On Tue, Jan 15, 2019 at 9:26 PM Christoph Hellwig wrote: > > On Thu, Dec 27, 2018 at 04:48:20PM +0530, Anup Patel wrote: > > We explicitly differentiate between PLIC handler and context because > > PLIC context is for given mode of HART whereas PLIC handler is per-CPU > >

Re: [PATCH v4 3/5] irqchip: sifive-plic: Add warning in plic_init() if handler already present

On Tue, Jan 15, 2019 at 9:24 PM Christoph Hellwig wrote: > > On Thu, Dec 27, 2018 at 04:48:19PM +0530, Anup Patel wrote: > > We have two enteries (one for M-mode and another for S-mode) in the > > interrupts-extended DT property of PLIC DT node for each HART. It is > >

Re: [PATCH v4 2/5] irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle()

On Tue, Jan 15, 2019 at 9:24 PM Christoph Hellwig wrote: > > On Thu, Dec 27, 2018 at 04:48:18PM +0530, Anup Patel wrote: > > The plic_toggle() uses raw_spin_lock() and plic_irq_toggle has a > > for loop so both these functions are not suitable for being inline > >

Re: [PATCH] tty/serial: use uart_console_write in the RISC-V SBL early console

On Thu, Jan 10, 2019 at 10:41 PM Andreas Schwab wrote: > > This enables proper NLCR processing. > > Suggested-by: Anup Patel > Signed-off-by: Andreas Schwab > --- > drivers/tty/serial/earlycon-riscv-sbi.c | 13 - > 1 file changed, 8 insertions(+), 5 del

Re: [PATCH] tty/serial: emit CR before NL in RISC-V SBL console

On Thu, Jan 10, 2019 at 8:56 PM Andreas Schwab wrote: > > On Jan 10 2019, Anup Patel wrote: > > > Instead of doing '\n' handling here, we should do it in BBL or > > OpenSBI (i.e. SBI runtime firmware) otherwise all users of > > SBI_CONSOLE_PUTCHAR (namely, Linux, Free

Re: [PATCH] tty/serial: emit CR before NL in RISC-V SBL console

On Thu, Jan 10, 2019 at 7:37 PM Andreas Schwab wrote: > > Signed-off-by: Andreas Schwab > --- > drivers/tty/serial/earlycon-riscv-sbi.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c >

Re: [PATCH v4 0/5] IRQ affinity support in PLIC driver

On Thu, Dec 27, 2018 at 4:48 PM Anup Patel wrote: > > This patchset primarily adds IRQ affinity support in PLIC driver and > other improvements. > > It gives mechanism for explicitly route external interrupts to particular > CPUs using smp_affinity attribute of each Linux IRQs

Re: [PATCH v2 8/8] RISC-V: Assign hwcap only according to current cpu.

if (!node) { > pr_warning("Unable to find \"cpu\" devicetree entry"); > return; > -- > 2.7.4 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 7/8] RISC-V: Check and continue in case of an invalid cpuid.

f (cpu < 0) { > + pr_warn("Invalid cpuid for context %d\n", i); > + continue; > + } > + > handler = per_cpu_ptr(_handlers, cpu); > handler->present = true; > handler->ctxid = i; > -- > 2.7.4 > Otherwise, looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 6/8] RISC-V: Add required checks during clock source init

> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", > + error); > return error; > } > > -- > 2.7.4 > Apart from above, looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 5/8] RISC-V: Compare cpuid with NR_CPUS before mapping.

[%d] for hartid [%d]\n", > + cpuid, hart); > + break; > + } > > cpuid_to_hartid_map(cpuid) = hart; > set_cpu_possible(cpuid, true); > -- > 2.7.4 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 4/8] RISC-V: Allow hartid-to-cpuid function to fail.

turn i; > > pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); > - BUG(); > return i; > } > > -- > 2.7.4 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

Re: [PATCH v2 3/8] RISC-V: Remove NR_CPUs check during hartid search from DT

pr_info("Found hart ID %d, which is above NR_CPUs. Disabling > this hart\n", hart); > - return -(ENODEV); > - } > > if (of_property_read_string(node, "status", )) { > pr_warn("CPU with hartid=%d has no \"status\" property\n", > hart); > -- > 2.7.4 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup

[PATCH 5/5] RISC-V: Implement compile-time fixed mappings

From: Anup Patel This patch implements compile-time virtual to physical mappings. These compile-time fixed mappings can be used by earlycon, ACPI, and early ioremap for creating fixed mappings when FIX_EARLYCON_MEM=y. To start with, we have enabled compile-time fixed mappings for earlycon

[PATCH 4/5] RISC-V: Move setup_vm() to mm/init.c

From: Anup Patel The setup_vm() is responsible for setting up initial page table hence should be placed in mm/init.c. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 49 -- arch/riscv/mm/init.c | 50 +++ 2

[PATCH 3/5] RISC-V: Move setup_bootmem() to mm/init.c

From: Anup Patel The setup_bootmem() mainly populates memblocks and does early memory reservations. The right location for this function is mm/init.c. Signed-off-by: Anup Patel --- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/setup.c| 48

[PATCH 2/5] RISC-V: Setup init_mm before parse_early_param()

From: Anup Patel We should setup init_mm before doing parse_early_param() in setup_arch() to be consistent with setup_arch() of other architectures such as x86, ARM, and ARM64. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 9 - 1 file changed, 4 insertions(+), 5 deletions

[PATCH 1/5] RISC-V: Move free_initrd_mem() to kernel/setup.c

From: Anup Patel We move free_initrd_mem() to kernel/setup.c so that all initrd related functions are in one place. Signed-off-by: Anup Patel --- arch/riscv/kernel/setup.c | 4 arch/riscv/mm/init.c | 7 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch

[PATCH 0/5] Fixmap support and MM cleanups

get early prints on QEMU virt machine without using SBI calls. The patchset is tested on QEMU virt machine. It is based on Linux-5.0-rc1 and can be found at riscv_fixmap_v1 branch of: https://github.com/avpatel/linux.git. Anup Patel (5): RISC-V: Move free_initrd_mem() to kernel/setup.c RISC-V: Set

[PATCH v4 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

693 77410 Rescheduling interrupts IPI1: 0 2 3 16 Function call interrupts Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 44 ++- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/driv

[PATCH v4 3/5] irqchip: sifive-plic: Add warning in plic_init() if handler already present

updated interrupts-extended DT property. Signed-off-by: Anup Patel Reviewed-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 01ffbcae..b9a0bcefe426

[PATCH v4 1/5] irqchip: sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 47

[PATCH v4 0/5] IRQ affinity support in PLIC driver

of PATCH4 Changes since v1: - Removed few whitspace changes from PATCH1 - Keep use of DEFINE_PER_CPU() as it is Anup Patel (5): irqchip: sifive-plic: Pre-compute context hart base and enable base irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle() irqchip: sifive-plic: Add

[PATCH v4 2/5] irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle()

The plic_toggle() uses raw_spin_lock() and plic_irq_toggle has a for loop so both these functions are not suitable for being inline hence this patch removes the inline keyword. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 6 +++--- 1 file changed, 3 insertions(+), 3

[PATCH v4 4/5] irqchip: sifive-plic: Differentiate between PLIC handler and context

uot;nr_contexts" and "nr_mapped" to "nr_handlers" in plic_init(). Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqc

Re: [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle()

On Wed, Dec 19, 2018 at 9:58 PM Christoph Hellwig wrote: > > On Tue, Dec 18, 2018 at 02:20:10PM +0530, Anup Patel wrote: > > Actually these functions should not be inline because plic_toggle() uses > > raw_spin_lock() and plic_irq_toggle() uses for-loop. > > So? It stil

Re: [PATCH 3/3] RISC-V: Fix non-smp kernel boot on SMP systems

On Thu, Dec 27, 2018 at 4:39 AM Atish Patra wrote: > > In non-smp configuration, hartid can be higher that NR_CPUS. > riscv_of_processor_hartid should not be compared to hartid to > NR_CPUS in that case. Moreover, this function checks all the > DT properties of a hart node. NR_CPUS comparison

Re: [PATCH 2/3] RISC-V: Move cpuid to hartid mapping to SMP.

S-1] = INVALID_HARTID > }; > @@ -91,6 +92,7 @@ void __init smp_setup_processor_id(void) > { > cpuid_to_hartid_map(0) = boot_cpu_hartid; > } > +#endif Please move __cpuid_to_hartid_map[] and smp_setup_processor_id() to arch/riscv/kernel/smp.c Otherwise, looks good to me. Reviewed-by: Anup Patel

Re: [PATCH 1/3] RISC-V: Do not wait indefinitely in __cpu_up

gt; } > > void __init smp_cpus_done(unsigned int max_cpus) > @@ -121,6 +128,7 @@ asmlinkage void __init smp_callin(void) > * a local TLB flush right now just in case. > */ > local_flush_tlb_all(); > + complete(_running); > /* >

Re: [PATCH] RISC-V: Make BSS section as the last section in vmlinux.lds.S

On Fri, Dec 21, 2018 at 2:10 AM Palmer Dabbelt wrote: > > On Mon, 17 Dec 2018 01:36:45 PST (-0800), a...@brainfault.org wrote: > > On Mon, Nov 26, 2018 at 11:42 AM Anup Patel wrote: > >> > >> The objcopy only emits loadable sections when creating flat kernel > &

[PATCH v2] RISC-V: Make BSS section as the last section in vmlinux.lds.S

. The flat kernel Image size of Linux-4.20-rc4 using GCC 8.2.0 is 8819980 bytes with current RISC-V vmlinux.lds.S and it reduces to 7991740 bytes with this patch applied. In summary, this patch reduces Linux-4.20-rc4 flat kernel Image size by 809 KB. Signed-off-by: Anup Patel --- Changes since v1

Re: [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

On Tue, Dec 18, 2018 at 12:02 AM Christoph Hellwig wrote: > > On Fri, Nov 30, 2018 at 01:32:07PM +0530, Anup Patel wrote: > > This patch provides irq_set_affinity() implementation for PLIC driver. > > It also updates irq_enable() such that PLIC interrupts are only enabled &

Re: [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle()

On Mon, Dec 17, 2018 at 11:57 PM Christoph Hellwig wrote: > > > -static inline void plic_toggle(struct plic_handler *handler, > > - int hwirq, int enable) > > +static void plic_toggle(struct plic_handler *handler, int hwirq, int > > enable) > > { > > u32

Re: [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present

On Mon, Dec 17, 2018 at 11:58 PM Christoph Hellwig wrote: > > On Fri, Nov 30, 2018 at 01:32:05PM +0530, Anup Patel wrote: > > We have two enteries (one for M-mode and another for S-mode) in the > > interrupts-extended DT property of PLIC DT node for each HART. It is > >

Re: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base

On Mon, Dec 17, 2018 at 11:55 PM Christoph Hellwig wrote: > > On Fri, Nov 30, 2018 at 01:32:02PM +0530, Anup Patel wrote: > > This patch does following optimizations: > > 1. Pre-compute hart base for each context handler > > 2. Pre-compute enable base for each context ha

Re: [PATCH v3 2/6] irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details

On Mon, Dec 17, 2018 at 11:54 PM Christoph Hellwig wrote: > > > +struct plic_hw { > > + u32 nr_irqs; > > + u32 nr_handlers; > > + u32 nr_mapped; > > + void __iomem*regs; > > + struct irq_domain

Re: [PATCH] RISC-V: Make BSS section as the last section in vmlinux.lds.S

On Mon, Dec 17, 2018 at 6:29 PM Nick Kossifidis wrote: > > Στις 2018-12-17 11:36, Anup Patel έγραψε: > > On Mon, Nov 26, 2018 at 11:42 AM Anup Patel > > wrote: > >> > >> The objcopy only emits loadable sections when creating flat kernel > >> Image.

Re: [PATCH v3 0/6] IRQ affinity support in PLIC driver

On Fri, Nov 30, 2018 at 1:32 PM Anup Patel wrote: > > This patchset primarily adds IRQ affinity support in PLIC driver and > other improvements. > > The patchset gives mechanism for explicitly routing external interrupts to > particular CPUs using smp_affinity attribute of eac

Re: [PATCH] RISC-V: Make BSS section as the last section in vmlinux.lds.S

On Mon, Nov 26, 2018 at 11:42 AM Anup Patel wrote: > > The objcopy only emits loadable sections when creating flat kernel > Image. To have minimal possible size of flat kernel Image, we should > have all non-loadable sections after loadable sections. > > Currently, execp

Re: [PATCH] clocksource: riscv_timer: Provide sched_clock

> default sched_clock. > > > > To avoid this, we explicity provide sched_clock using RISC-V rdtime > > instruction (similar to riscv_timer clocksource). > > > > Signed-off-by: Anup Patel > > --- > > drivers/clocksource/riscv_timer.c | 9 +

Re: [PATCH] clocksource: riscv_timer: Provide sched_clock

> default sched_clock. > > > > To avoid this, we explicity provide sched_clock using RISC-V rdtime > > instruction (similar to riscv_timer clocksource). > > > > Signed-off-by: Anup Patel > > --- > > drivers/clocksource/riscv_timer.c | 9 +

[PATCH 2/3] RISC-V: defconfig: Enable RISC-V SBI earlycon support

This patch enables RISC-V SBI earlycon support in default defconfig so that we can use "earlycon=sbi" in kernel parameters for early debug prints. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defcon

[PATCH 2/3] RISC-V: defconfig: Enable RISC-V SBI earlycon support

This patch enables RISC-V SBI earlycon support in default defconfig so that we can use "earlycon=sbi" in kernel parameters for early debug prints. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defcon

[PATCH 3/3] RISC-V: Remove EARLY_PRINTK support

The EARLY_PRINTK using SBI console calls is not required any more because we now have RISC-V SBI support in generic earlycon framework. Signed-off-by: Anup Patel --- arch/riscv/Kconfig.debug | 2 -- arch/riscv/kernel/setup.c | 28 2 files changed, 30 deletions

[PATCH 3/3] RISC-V: Remove EARLY_PRINTK support

The EARLY_PRINTK using SBI console calls is not required any more because we now have RISC-V SBI support in generic earlycon framework. Signed-off-by: Anup Patel --- arch/riscv/Kconfig.debug | 2 -- arch/riscv/kernel/setup.c | 28 2 files changed, 30 deletions

[PATCH 1/3] tty/serial: Add RISC-V SBI earlycon support

In RISC-V, the M-mode runtime firmware provide SBI calls for debug prints. This patch adds earlycon support using RISC-V SBI console calls. To enable it, just pass "earlycon=sbi" in kernel parameters. Signed-off-by: Anup Patel --- drivers/tty/serial/Kconfig

[PATCH 1/3] tty/serial: Add RISC-V SBI earlycon support

In RISC-V, the M-mode runtime firmware provide SBI calls for debug prints. This patch adds earlycon support using RISC-V SBI console calls. To enable it, just pass "earlycon=sbi" in kernel parameters. Signed-off-by: Anup Patel --- drivers/tty/serial/Kconfig

[PATCH 0/3] RISC-V SBI earlycon

QEMU virt machine. It is based on Linux-4.20-rc5 and can be found at riscv_earlycon_v1 branch of: https://github.com/avpatel/linux.git Anup Patel (3): tty/serial: Add RISC-V SBI earlycon support RISC-V: defconfig: Enable RISC-V SBI earlycon support RISC-V: Remove EARLY_PRINTK support

[PATCH 0/3] RISC-V SBI earlycon

QEMU virt machine. It is based on Linux-4.20-rc5 and can be found at riscv_earlycon_v1 branch of: https://github.com/avpatel/linux.git Anup Patel (3): tty/serial: Add RISC-V SBI earlycon support RISC-V: defconfig: Enable RISC-V SBI earlycon support RISC-V: Remove EARLY_PRINTK support

[PATCH v2 1/2] RISC-V: Select GENERIC_SCHED_CLOCK for clocksource drivers

The riscv_timer driver can provide sched_clock using "rdtime" instruction but to achieve this we require generic sched_clock framework hence this patch selects GENERIC_SCHED_CLOCK for RISCV. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)

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