, 2019 at 1:02 PM Daniel Baluta wrote:
>
> Some of i.MX8 processors (e.g i.MX8QM, i.MX8QXP) contain
> the Tensilica HiFi4 DSP for advanced pre- and post-audio
> processing.
>
> The communication between Host CPU and DSP firmware is
> taking place using a shared memory are
On Wed, Aug 7, 2019 at 6:28 PM Daniel Baluta wrote:
>
> On Wed, Aug 7, 2019 at 6:22 PM Pierre-Louis Bossart
> wrote:
> >
> >
> > >>>> +static int sof_dt_probe(struct platform_device *pdev)
> > >>>> +{
> > >>>> +
Add dummy support for SAI/ESAI digital audio interface
IPs found on i.MX8 boards.
Signed-off-by: Daniel Baluta
---
include/sound/sof/dai.h | 2 ++
include/uapi/sound/sof/tokens.h | 8
sound/soc/sof/topology.c| 30 ++
3 files changed, 40
This includes DSP reserved memory, ADMA DSP device and DSP MU
communication channels description.
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi| 32 +++
2 files changed, 36 insertions
This describes the DSP device tree node.
Signed-off-by: Daniel Baluta
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dsp/fsl,dsp.yaml | 88 +++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
diff --git
Add support for the audio DSP hardware found on NXP i.MX8 platform.
Signed-off-by: Daniel Baluta
---
sound/soc/sof/Kconfig | 1 +
sound/soc/sof/Makefile | 1 +
sound/soc/sof/imx/Kconfig | 22 +++
sound/soc/sof/imx/Makefile | 4 +
sound/soc/sof/imx/imx8.c | 394
Add support for device tree based SOF DSP devices.
Signed-off-by: Daniel Baluta
---
sound/soc/sof/Kconfig | 10 +++
sound/soc/sof/Makefile | 3 +
sound/soc/sof/sof-of-dev.c | 143 +
3 files changed, 156 insertions(+)
create mode 100644 sound/soc
hes will not be selected.
[1] https://github.com/thesofproject/sof
[2] https://github.com/thesofproject/linux/pull/1048/commits
Daniel Baluta (5):
ASoC: SOF: Add OF DSP device support
ASoC: SOF: imx: Add i.MX8 HW support
ASoC: SOF: topology: Add dummy support for i.MX8 DAIs
arm64: dts: imx8qxp: Add DSP
On Tue, Jul 23, 2019 at 6:19 PM Pierre-Louis Bossart
wrote:
>
>
> > diff --git a/sound/soc/sof/Kconfig b/sound/soc/sof/Kconfig
> > index 61b97fc55bb2..2aa3a1cdf60c 100644
> > --- a/sound/soc/sof/Kconfig
> > +++ b/sound/soc/sof/Kconfig
> > @@ -36,6 +36,15 @@ config SND_SOC_SOF_ACPI
> > Say
On Wed, Aug 7, 2019 at 6:22 PM Pierre-Louis Bossart
wrote:
>
>
> +static int sof_dt_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + const struct sof_dev_desc *desc;
> + /*TODO: create a generic snd_soc_xxx_mach */
> +
On Wed, Jul 24, 2019 at 10:04 AM Daniel Baluta wrote:
>
> On Tue, Jul 23, 2019 at 6:19 PM Pierre-Louis Bossart
> wrote:
> >
> >
> > > diff --git a/sound/soc/sof/Kconfig b/sound/soc/sof/Kconfig
> > > index 61b97fc55bb2..2aa3a1cdf60c 100644
> > > -
On Mon, Jul 29, 2019 at 11:22 PM Nicolin Chen wrote:
>
> On Sun, Jul 28, 2019 at 10:24:25PM +0300, Daniel Baluta wrote:
> > SAI supports up to 8 Rx/Tx data lines which can be enabled
> > using TCE/RCE bits of TCR3/RCR3 registers.
> >
> > Data lines to be enable
llow users to set it.
Daniel Baluta (5):
ASoC: fsl_sai: Add registers definition for multiple datalines
ASoC: fsl_sai: Update Tx/Rx channel enable mask
ASoC: fsl_sai: Add support for SAI new version
ASoC: fsl_sai: Add support for imx7ulp/imx8mq
ASoC: dt-bindings: Introduce compatib
, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 76 +++--
sound/soc/fsl/fsl_sai.h | 36 ---
2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta
Acked-by: Nicolin Chen
---
sound/soc/fsl
-off-by: Daniel Baluta
[adapted to linux-next]
---
sound/soc/fsl/fsl_sai.c | 228
sound/soc/fsl/fsl_sai.h | 41
2 files changed, 156 insertions(+), 113 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 637b1d12a575
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile
strings to differentiate this.
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.
Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.
Signed-off-by: Daniel Baluta
---
sound/soc
On Tue, Jul 30, 2019 at 10:59 AM Nicolin Chen wrote:
>
> On Mon, Jul 29, 2019 at 09:20:01PM +0100, Mark Brown wrote:
> > On Mon, Jul 29, 2019 at 10:57:43PM +0300, Daniel Baluta wrote:
> > > On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen
> > > wrote:
> > &g
On Tue, 2019-08-06 at 14:46 +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> When of_clk_add_provider failed, all clks should be unregistered.
>
> Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
> ---
> drivers/clk/imx/clk-imx8mq.c | 10 +-
On Tue, 2019-08-06 at 14:46 +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> When of_clk_add_provider failed, all clks should be unregistered.
>
> Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
Thanks Anson for the patch!
t; SR/CR registers are defined at 0x60/0x64.
> Extend this driver to support it.
>
> Signed-off-by: Richard Zhu
> Suggested-by: Oleksij Rempel
> Reviewed-by: Dong Aisheng
> Reviewed-by: Oleksij Rempel
Very clean solution. Thanks Richard!
Reviewed-by: Daniel Baluta
> --
+ Rob
On Mon, Aug 5, 2019 at 8:18 AM Richard Zhu wrote:
>
> There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible
> to support it.
>
> Signed-off-by: Richard Zhu
> Reviewed-by: Dong Aisheng
Reviewed-by: Daniel Baluta
> ---
> Documentati
One more thing. See below:
On Wed, Jul 31, 2019 at 12:14 PM Richard Zhu wrote:
> -/* Control Register */
> -#define IMX_MU_xCR 0x24
> /* General Purpose Interrupt Enable */
> #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
> /* Receive Interrupt Enable */
> @@ -44,6 +36,13
Hi Oleksij,
Thanks for review
>
> your patch is in conflicht with Richard's Zhu
> patch "[PATCH v3] mailbox: imx: add support for imx v1 mu".
> Please sync your works.
Sent an email to Richard. Hopefully he can rebase his change on my patches.
>
> Looks like here is one more bug "from the
bugfixes attached?
thanks,
Daniel.
From f9f382b8cab2cf88abf7fb26b885ac96e0cbaff4 Mon Sep 17 00:00:00 2001
From: Daniel Baluta
Date: Thu, 1 Aug 2019 17:41:25 +0300
Subject: [PATCH 2/2] mailbox: imx: Clear the right interrupts at shutdown
Make sure to only clear enabled interrupts keeping count
On Tue, Jul 23, 2019 at 10:47 AM Shawn Guo wrote:
>
> On Tue, Jul 23, 2019 at 10:44:09AM +0300, Daniel Baluta wrote:
> > Just realized that for this patch I forgot to add [PATCH v3]. Shawn,
> > should I resend?
>
> No need.
Just sent v4 out there adding support for remove
:
.handle_reply
.handle_request
- the callbacks will be used by the protocol on
notification arrival from DSP.
Signed-off-by: Daniel Baluta
---
Changes since v3:
- Added remove function
drivers/firmware/imx/Kconfig | 11 +++
drivers/firmware/imx/Makefile| 1
.2+0x24/0xb8
[2.116453] mbox_free_channel+0x18/0x28
This bug is present from the beginning of times.
Cc: Oleksij Rempel
Fixes: 2bb7005696e2246 ("mailbox: Add support for i.MX messaging unit")
Signed-off-by: Daniel Baluta
---
drivers/mailbox/imx-mailbox.c | 4 +++-
1 file
On Tue, Jul 30, 2019 at 3:05 PM Mark Brown wrote:
>
> On Tue, Jul 30, 2019 at 03:02:30PM +0300, Daniel Baluta wrote:
>
> > I removed the 'or' on purpose because I don't want to move it
> > around each time we add a new compatible.
>
> > Anyhow, I can put it back if t
On Tue, Jul 30, 2019 at 11:02 AM Nicolin Chen wrote:
>
> On Sun, Jul 28, 2019 at 10:24:29PM +0300, Daniel Baluta wrote:
> > For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile
> > strings to differentiate this.
> >
> > Signed-off-by: Daniel Balu
On Mon, Jul 29, 2019 at 11:15 PM Nicolin Chen wrote:
>
> On Sun, Jul 28, 2019 at 10:24:26PM +0300, Daniel Baluta wrote:
> > SAI supports up to 8 data lines. This property let the user
> > configure how many data lines should be used per transfer
> > direction (Tx/Rx).
&g
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen wrote:
>
> On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
> > SAI IP supports up to 8 data lines. The configuration of
> > supported number of data lines is decided at SoC integration
> > time.
> >
&
On Mon, 2019-07-29 at 16:39 +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> Some platforms have clock control for TMU, add optional
> clocks property to the binding doc.
>
> Signed-off-by: Anson Huang
Please also pick Rob's Reviewed-by from last revision.
> ---
> No changes.
> ---
On Mon, Jul 29, 2019 at 11:32 AM Guido Günther wrote:
>
> Hi,
> On Sun, Jul 28, 2019 at 05:12:18PM +0300, Daniel Baluta wrote:
> > From: Abel Vesa
> >
> > Add the initial configuration for clocks that need default parent and rate
> > setting. This is based
On Mon, Jul 29, 2019 at 10:49 AM Anson Huang wrote:
> > We are all set then. Thanks Anson for clarifications!
>
> Thanks, so we are all clear about this issue, need to wait thermal maintainer
> to review
> the rest patch in this series, but I did NOT receive any response from
> thermal
On Mon, Jul 29, 2019 at 10:20 AM Daniel Baluta wrote:
>
>
> > > Your explanation makes a lot of sense. We will take care today of Abel's
> > > patch.
> > > What do you think about Fabio's patch? I also think this is a valid patch:
> > >
>
>
> &
> > Your explanation makes a lot of sense. We will take care today of Abel's
> > patch.
> > What do you think about Fabio's patch? I also think this is a valid patch:
> >
>
> Hmm, when did Fabio sent out this patch? I can NOT find it...
> I also have a patch in this series (#4/6) doing same
On Mon, Jul 29, 2019 at 4:29 AM Anson Huang wrote:
>
> Hi, Abel/Daniel
>
> > On 19-07-27 09:33:10, Daniel Baluta wrote:
> > > On Sat, Jul 27, 2019 at 9:19 AM Anson Huang
> > wrote:
> > > >
> > > > Hi, Daniel
> > > >
> >
, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 76 +++--
sound/soc/fsl/fsl_sai.h | 36 ---
2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl
Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.
Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.
Signed-off-by: Daniel Baluta
---
sound/soc
-off-by: Daniel Baluta
[adapted to linux-next]
---
sound/soc/fsl/fsl_sai.c | 230
sound/soc/fsl/fsl_sai.h | 41 +++
2 files changed, 157 insertions(+), 114 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 5e7cb7fd29f5
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile
strings to differentiate this.
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 14
SAI supports up to 8 data lines. This property let the user
configure how many data lines should be used per transfer
direction (Tx/Rx).
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
SAI supports up to 8 Rx/Tx data lines which can be enabled
using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property.
By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c
each call of regmap_functions.
Daniel Baluta (7):
ASoC: fsl_sai: Add registers definition for multiple datalines
ASoC: fsl_sai: Update Tx/Rx channel enable mask
ASoC: fsl_sai: Add support to enable multiple data lines
ASoC: dt-bindings: Document dl-mask property
ASoC: fsl_sai: Add suppo
On Sun, Jul 28, 2019 at 5:53 PM Angus Ainslie wrote:
>
> Hi Daniel,
>
> On 2019-07-28 07:12, Daniel Baluta wrote:
> > From: Abel Vesa
> >
> > Add the initial configuration for clocks that need default parent and
> > rate
> > setting. This is based
On Wed, Jul 3, 2019 at 4:05 PM Daniel Baluta wrote:
>
> On Wed, Jul 3, 2019 at 3:03 PM Abel Vesa wrote:
> >
> > Add the initial configuration for clocks that need default parent and rate
> > setting. This is based on the vendor tree clock provider parents and rates
that by adding the initial rate setting for audio_pll1/audio_pll
setting we need to remove it from imx8mq-librem5-devkit.dts
Signed-off-by: Abel Vesa
Signed-off-by: Daniel Baluta
Tested-by: Angus Ainslie (Purism)
---
Changes since v3:
- fix extra new lines
.../dts/freescale/imx8mq-librem5
that by adding the initial rate setting for audio_pll1/audio_pll
setting we need to remove it from imx8mq-librem5-devkit.dts
imx8mq-librem5-devkit.dts
Signed-off-by: Abel Vesa
Signed-off-by: Daniel Baluta
---
Changes since v2:
- set rate for audio_pll1/audio_pll2 in the dtsi file
Making audio_pll1 parent of audio_pll1_bypass, will allow
setting rates multiple of 8000 for children.
After unbypass clk hierarchy looks like this:
* osc_25m
* audio_pll1
* audio_pll1_bypass
* audio_pll1_out
* sai2
* sai2_root_clk
Signed-off-by: Daniel Baluta
On Sat, Jul 27, 2019 at 9:19 AM Anson Huang wrote:
>
> Hi, Daniel
>
> > Subject: Re: [PATCH 5/6] clk: imx8mq: Remove CLK_IS_CRITICAL flag for
> > IMX8MQ_CLK_TMU_ROOT
> >
> > Hi all,
> >
> > latest linux-next hangs at boot.
> >
> > commit fde50b96be821ac9673a7e00847cc4605bd88f34 (HEAD -> master,
explanatory, because nothing on this line says "bus"
> and it could be that someone reading this code isn't well versed in the
> concepts of ARM world AHB to connect the two.
Agree with Stephen. Commit message should try to give as much details
as possible
also maybe educate the readers who might not have that much knowledge.
Abel, I understand that for someone who works daily with this part of the kernel
this change might look trivial.
Also, without this patch linux-next hangs on imx8mq.
With the explanation added you can add my:
Tested-by: Daniel Baluta
thanks,
Daniel.
Hi all,
latest linux-next hangs at boot.
commit fde50b96be821ac9673a7e00847cc4605bd88f34 (HEAD -> master, tag:
next-20190726, origin/master, origin/HEAD)
Author: Stephen Rothwell
Date: Fri Jul 26 15:18:02 2019 +1000
Add linux-next specific files for 20190726
Signed-off-by: Stephen
On Thu, Jul 25, 2019 at 2:14 AM Nicolin Chen wrote:
>
> On Mon, Jul 22, 2019 at 03:48:29PM +0300, Daniel Baluta wrote:
> > SAI supports up to 8 data lines. This property let the user
> > configure how many data lines should be used per transfer
> > direction (Tx/Rx).
>
On Thu, Jul 25, 2019 at 2:32 AM Nicolin Chen wrote:
>
> On Mon, Jul 22, 2019 at 03:48:32PM +0300, Daniel Baluta wrote:
> > New IP version introduces Version ID and Parameter registers
> > and optionally added Timestamp feature.
> >
> > VERID and PARAM registers are
On Thu, Jul 25, 2019 at 2:22 AM Nicolin Chen wrote:
>
> On Mon, Jul 22, 2019 at 03:48:31PM +0300, Daniel Baluta wrote:
> > This allows combining multiple-data-line FIFOs into a
> > single-data-line FIFO.
> >
> > Signed-off-by: Daniel Baluta
> > ---
> >
On Thu, Jul 25, 2019 at 1:34 AM Nicolin Chen wrote:
>
> On Mon, Jul 22, 2019 at 03:48:24PM +0300, Daniel Baluta wrote:
> > From: Lucas Stach
> >
> > New revisions of the SAI IP block have even more differences that need
> > be taken into account by the driver.
On Wed, Jul 24, 2019 at 11:32 AM Lucas Stach wrote:
>
> Hi Daniel,
>
> Am Mittwoch, den 24.07.2019, 09:54 +0300 schrieb Daniel Baluta:
> > On Tue, Jul 23, 2019 at 6:18 PM Pierre-Louis Bossart
> [...]
> >
> > > Also are all the resources device-managed, I don'
On Mon, Jul 22, 2019 at 3:58 PM Lucas Stach wrote:
>
> Am Montag, den 22.07.2019, 15:48 +0300 schrieb Daniel Baluta:
> > SAI supports up to 8 Rx/Tx data lines which can be enabled
> > using TCE/RCE bits of TCR3/RCR3 registers.
> >
> > Data lines to be enabled are rea
latforms
> > Say Y if you have such a device.
> > diff --git a/sound/soc/sof/sof-dt-dev.c b/sound/soc/sof/sof-dt-dev.c
> > new file mode 100644
> > index ..31429bbb5c7e
> > --- /dev/null
> > +++ b/sound/soc/sof/sof-dt-dev.c
> > @@ -0,0 +1
On Tue, Jul 23, 2019 at 6:18 PM Pierre-Louis Bossart
wrote:
>
>
> > diff --git a/sound/soc/sof/imx/Makefile b/sound/soc/sof/imx/Makefile
> > new file mode 100644
> > index ..c69237971da5
> > --- /dev/null
> > +++ b/sound/soc/sof/imx/Makefile
> > @@ -0,0 +1,7 @@
> > +#
On Tue, Jul 23, 2019 at 8:01 PM Mark Brown wrote:
>
> On Mon, Jul 22, 2019 at 03:48:24PM +0300, Daniel Baluta wrote:
> > From: Lucas Stach
> >
> > New revisions of the SAI IP block have even more differences that need
> > be taken into account by the driver.
This includes DSP reserved memory, ADMA DSP device and DSP MU
communication channels description.
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi| 32 +++
2 files changed, 36 insertions
Add support for device tree based SOF DSP devices.
Signed-off-by: Daniel Baluta
---
This is also on review with SOF community here:
https://github.com/thesofproject/linux/pull/1048
sound/soc/sof/Kconfig | 9 +++
sound/soc/sof/Makefile | 3 +
sound/soc/sof/imx/Kconfig | 1
Add dummy support for SAI/ESAI digital audio interface
IPs found on i.MX8 boards.
Signed-off-by: Daniel Baluta
---
This is also on review with SOF community here:
https://github.com/thesofproject/linux/pull/1048
include/sound/sof/dai.h | 2 ++
include/uapi/sound/sof/tokens.h | 8
This describes the DSP device tree node.
Signed-off-by: Daniel Baluta
---
.../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
diff --git a/Documentation/devicetree
Add support for the audio DSP hardware found on NXP i.MX8 platform.
Signed-off-by: Daniel Baluta
---
- This is also on review with SOF community here:
https://github.com/thesofproject/linux/pull/1048
sound/soc/sof/Kconfig | 1 +
sound/soc/sof/Makefile | 1 +
sound/soc/sof/imx
' as it was already
applied by Shawn
- add patches adding support for Linux DSP driver to make things
clear for review
- add maxItems property for PM in DT bindings doc
Daniel Baluta (5):
ASoC: SOF: imx: Add i.MX8 HW support
ASoC: SOF: topology: Add dummy support
Just realized that for this patch I forgot to add [PATCH v3]. Shawn,
should I resend?
Oleksij, care to have a look at this v3. It has a minor modification
but basically
all your review in v1 is still addressed.
On Thu, Jul 18, 2019 at 11:21 AM Daniel Baluta wrote:
>
> Some of i.MX8 proc
On Mon, Jul 22, 2019 at 9:30 PM Vaittinen, Matti
wrote:
>
> Sorry for top posting. I'm replying using mobile phone and outlook web app...
>
> gpio_intr is not needed. Irq must be given using the standard irq property.
> gpio_intr has been used in an old draft driver - I assume the dts originates
Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.
Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.
Signed-off-by: Daniel Baluta
---
sound/soc
From: Lucas Stach
The DMA request schould be triggered as soon as the FIFO has space
for another burst. As different versions of the SAI block have
different FIFO sizes, the watrmark level needs to be derived from
version specific data.
Signed-off-by: Lucas Stach
---
sound/soc/fsl/fsl_sai.c |
SAI supports up to 8 data lines. This property let the user
configure how many data lines should be used per transfer
direction (Tx/Rx).
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation
with data line #0.
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 10 +-
sound/soc/fsl/fsl_sai.h | 6 --
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 768341608695..d0fa02188b7c 100644
--- a/sound/soc
each board private data.
[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7=.pdf
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 240 +++-
sound/soc/fsl/fsl_sai.h
mode is read from fsl,fcomb-mode
DT property. By default, if no property is specified fifo combine mode
is disabled.
[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7=.pdf
Signed-off-by: Daniel Baluta
---
sound
This allows combining multiple-data-line FIFOs into a
single-data-line FIFO.
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt
b/Documentation
, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 76 +++--
sound/soc/fsl/fsl_sai.h | 36 ---
2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 14
From: Lucas Stach
New revisions of the SAI IP block have even more differences that need
be taken into account by the driver. To avoid sprinking compatible
checks all over the driver move the current differences into of_match_data.
Signed-off-by: Lucas Stach
---
sound/soc/fsl/fsl_sai.c | 22
address space.
Patch 10 enable SAI for imx7ulp and imx8mq.
This patch introduces
Daniel Baluta (8):
ASoC: fsl_sai: Add registers definition for multiple datalines
ASoC: fsl_sai: Update Tx/Rx channel enable mask
ASoC: fsl_sai: Add support to enable multiple data lines
ASoC: dt-bindings: Document
On Fri, Jul 19, 2019 at 2:22 PM Fabio Estevam wrote:
>
> Hi Andra,
>
> On Fri, Jul 19, 2019 at 7:48 AM andradanciu1997
> wrote:
>
> > + pmic: pmic@4b {
> > + reg = <0x4b>;
> > + compatible = "rohm,bd71837";
> > + /* PMIC BD71837 PMIC_nINT
On Fri, Jul 19, 2019 at 10:00 AM Marco Felsch wrote:
>
> Hi Daniel,
>
> thanks for your patches :) but it's quite common to bundle the driver
> related and the dt related patches. Can you add the firmware related
> patch to this series in your v2?
Sure. Will do that in v2.
On Thu, Jul 18, 2019 at 9:40 PM Leonard Crestez wrote:
>
> On 18.07.2019 21:24, Daniel Baluta wrote:
> > On Thu, Jul 18, 2019 at 7:41 PM Rob Herring wrote:
> >>
> >> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta
> >> wrote:
> >>
On Thu, Jul 18, 2019 at 7:41 PM Rob Herring wrote:
>
> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta wrote:
> >
> > This describes the DSP device tree node.
> >
> > Signed-off-by: Daniel Baluta
> > ---
> > .../devicetree/bindings/dsp/fsl,dsp.yaml
i.MX8QXP contains Hifi4 DSP. There are four clocks
associated with DSP:
* dsp_lpcg_core_clk
* dsp_lpcg_ipg_clk
* dsp_lpcg_adb_aclk
* ocram_lpcg_ipg_clk
Signed-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 +
include/dt-bindings/clock
This describes the DSP device tree node.
Signed-off-by: Daniel Baluta
---
.../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
diff --git a/Documentation/devicetree
/thesofproject/sof
[2] https://github.com/thesofproject/linux/pull/1048/commits
Daniel Baluta (3):
clk: imx8: Add DSP related clocks
arm64: dts: imx8qxp: Add DSP DT node
dt-bindings: dsp: fsl: Add DSP core binding support
.../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++
arch
This includes DSP reserved memory, ADMA DSP device and DSP MU
communication channels description.
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi| 32 +++
2 files changed, 36 insertions
The DSP interrupt steer gathers interrupts from the system
and can be used to steer them to DSP.
Signed-off-by: Daniel Baluta
Reviewed-by: Dong Aisheng
---
drivers/firmware/imx/scu-pd.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu
ate with SCU and to keep things simple we don't
want that now.
Signed-off-by: Daniel Baluta
---
drivers/firmware/imx/scu-pd.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index 950d30238186..eb9700b66a76 100644
--- a/drivers/firm
add PD range for mu 13 side B
Daniel Baluta (3):
firmware: imx: scu-pd: Rename mu PD range to mu_a
firmware: imx: scu-pd: Add mu13 b side PD range
firmware: imx: scu-pd: Add IRQSTR_DSP PD range
drivers/firmware/imx/scu-pd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--
2.17.1
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages through the MU interface.
MUs have 2 “sides” with independent programming interfaces. Rename
mu PD range to mu_a because it's actually side A of MUs.
Signed-off-by: Daniel Baluta
:
.handle_reply
.handle_request
- the callbacks will be used by the protocol on
notification arrival from DSP.
Signed-off-by: Daniel Baluta
---
Changes since v2:
- remove DSP IPC own DT node as per Rob comments
- make dsp responsability to add MU nodes
I just made some minor changes and will send the patch right now.
Shawn please skip this.
On Tue, Jul 9, 2019 at 3:02 PM Oleksij Rempel wrote:
>
> On Tue, Jul 09, 2019 at 08:48:20AM +0300, Daniel Baluta wrote:
> > Hi Oleksij,
> >
> > Any comments on this?
>
On Thu, Jul 18, 2019 at 6:30 AM Aisheng Dong wrote:
>
> > From: Daniel Baluta
> > Sent: Thursday, July 4, 2019 3:04 AM
> > Subject: [PATCH 2/3] firmware: imx: scu-pd: Add mu_b side PD range
> >
> > LSIO subsystem contains 14 MU instances.
> >
>
Aisheng/Shengjiu,
Care to help with review on this?
On Wed, Jul 3, 2019 at 10:06 PM Daniel Baluta wrote:
>
> This patch adds power domain range for MU side b and irqsteer in
> preparation for adding support for DSP <-> AP IPC communication.
>
> Daniel Baluta (3):
>
Aisheng/Jacky,
Can you help with review on this?
On Tue, Jul 2, 2019 at 6:22 PM Daniel Baluta wrote:
>
> i.MX8QXP contains Hifi4 DSP. There are four clocks
> associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_i
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