- Dilip Kota
+select:
+ properties:
+compatible:
+ contains:
+const: intel,lgm-pcie
+ required:
+- compatible
+
properties:
compatible:
items:
Reviewed-by: Dilip Kota
Regards,
Dilip
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 7d98585860d845e36ee612832a5ff021f201dbaf
Gitweb:
https://git.kernel.org/tip/7d98585860d845e36ee612832a5ff021f201dbaf
Author:Dilip Kota
AuthorDate:Mon, 03 Aug 2020 15:56:36 +08:00
Committer
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 287bad1f2b30253443e61ff6d5597a76787f736a
Gitweb:
https://git.kernel.org/tip/287bad1f2b30253443e61ff6d5597a76787f736a
Author:Dilip Kota
AuthorDate:Mon, 03 Aug 2020 15:56:36 +08:00
Committer
Mountain SoC frequency
descriptor.
Fixes: 0cc5359d8fd45 ("x86/cpu: Update init data for new Airmont CPU model")
Fixes: 812c2d7506fd ("x86/tsc_msr: Use named struct initializers")
Signed-off-by: Dilip Kota
Reviewed-by: Andy Shevchenko
---
Changes on v3:
Fix the nit pick p
Mountain SoC frequency
descriptor.
Fixes: 0cc5359d8fd45 ("x86/cpu: Update init data for new Airmont CPU model")
Fixes: 812c2d7506fd ("x86/tsc_msr: Use named struct initializers")
Signed-off-by: Dilip Kota
---
Changes on v2:
Add description in the comments explaining about frequ
On 7/30/2020 3:57 PM, Andy Shevchenko wrote:
While at this, can you confirm (with maybe good description and
documentation reference) that the numbers in that array are all
correct?
Sure, i will add the description.
Regards,
Dilip
Mountain SoC frequency
descriptor.
Fixes: 0cc5359d8fd45 ("x86/cpu: Update init data for new Airmont CPU model")
Fixes: 812c2d7506fd ("x86/tsc_msr: Use named struct initializers")
Signed-off-by: Dilip Kota
---
arch/x86/kernel/tsc_msr.c | 3 ++-
1 file changed, 2 insertions(+),
On newer chipsets interrupt need to be acknowledged as they use
different interrupt controller which does not acknowledge the
interrupts automatically.
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-ssc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi
Existing driver supports only single core SoC. New multicore platforms uses
the same driver/IP so SMP support is required. This patch adds multicore
support in the driver.
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-ssc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
In full duplex mode, rx overflow error is observed. To overcome the error,
wait until the complete data got received and proceed further.
Fixes: 17f84b793c01 ("spi: lantiq-ssc: add support for Lantiq SSC SPI
controller")
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-
Add support to SPI controller on Intel Atom based Lightning Mountain
SoC which reuses the Lantiq SPI controller IP.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
.../devicetree/bindings/spi/spi-lantiq-ssc.txt | 21 +++--
1 file changed, 19 insertions(+), 2
Address of Interrupt control registers are different on new chipsets.
So move them to SoC specific data structure.
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-ssc.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-lantiq-ssc.c b
Moving interrupt configuration to SoC specific data structure helps to add
support for newer SoCs on which SPI controller with lesser interrupt lines
compared to existing chipsets.
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-ssc.c | 64 +++-
1
Add support to SPI controller on Intel Atom based Lightning Mountain SoC
which reuses Lantiq SPI controller IP.
Signed-off-by: Dilip Kota
---
drivers/spi/Kconfig | 4 ++--
drivers/spi/spi-lantiq-ssc.c | 40
2 files changed, 42 insertions(+), 2
On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.
Signed-off-by: Dilip Kota
---
drivers/spi/spi-lantiq-ssc.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/spi
On 5/6/2020 3:40 PM, Dilip Kota wrote:
On 5/5/2020 7:23 PM, Mark Brown wrote:
On Mon, May 04, 2020 at 06:15:47PM +0800, Dilip Kota wrote:
On 4/29/2020 8:13 PM, Mark Brown wrote:
I just tried to get the history of removing workqueue in SPI driver, on
GRX500 (earlier chipset of LGM) the SPI
On 6/10/2020 9:05 PM, Guenter Roeck wrote:
On 6/10/20 12:54 AM, Dilip Kota wrote:
On 6/9/2020 9:46 PM, Guenter Roeck wrote:
On 6/9/20 1:57 AM, Dilip Kota wrote:
On 6/8/2020 9:37 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
[...]
+
+description: |
+ Intel Lightning
On 6/9/2020 9:46 PM, Guenter Roeck wrote:
On 6/9/20 1:57 AM, Dilip Kota wrote:
On 6/8/2020 9:37 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
Add YAML schemas for the watchdog timer on Intel Lightning
Mountain SoC.
Signed-off-by: Dilip Kota
---
.../bindings/watchdog
On 6/8/2020 9:37 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
Add YAML schemas for the watchdog timer on Intel Lightning
Mountain SoC.
Signed-off-by: Dilip Kota
---
.../bindings/watchdog/intel,lgm-gptc-wdt.yaml | 75 ++
1 file changed, 75
On 6/8/2020 9:36 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
On Intel Lightning Mountain SoC, General Purpose Timer Counter(GPTC)
programmable as clocksource, real time clock or watchdog timer.
This driver configures GPTC as Watchdog timer and triggers reset signal
to CPU
This patch series adds watchdog timer driver and respective yaml schemas
for watchdog timer on Intel Lightning Mountain SoC.
This patch series is rebased and tested on mainline linux kernel 5.7:
base-commit: 3d77e6a8804a ("Linux 5.7")
tags: v5.7
Dilip Kota (2):
dt-bindings: watch
Add YAML schemas for the watchdog timer on Intel Lightning
Mountain SoC.
Signed-off-by: Dilip Kota
---
.../bindings/watchdog/intel,lgm-gptc-wdt.yaml | 75 ++
1 file changed, 75 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/intel,lgm-gptc
On Intel Lightning Mountain SoC, General Purpose Timer Counter(GPTC)
programmable as clocksource, real time clock or watchdog timer.
This driver configures GPTC as Watchdog timer and triggers reset signal
to CPU on timeout.
Signed-off-by: Dilip Kota
---
drivers/watchdog/Kconfig
with one of the switch case values, it
never hits the default case, so I didn't add the default case.)
This patch looks good to fix the warnings.
Reviewed-by: Dilip Kota
Regards,
Dilip
EP
reg_val |= FIELD_PREP(mask, val);
^~
Fixes: ac0a95a3ea78 ("phy: intel: Add driver support for ComboPhy")
Signed-off-by: Dilip Kota
Reported-by: kbuild test robot
Reported-by: Randy Dunlap
---
drivers/phy/intel/phy-intel-combo.c | 10 +-
1 file change
~~~
Fixes: ac0a95a3ea78 ("phy: intel: Add driver support for ComboPhy")
Signed-off-by: Dilip Kota
Reported-by: kbuild test robot
---
drivers/phy/intel/phy-intel-combo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/intel/phy-intel-combo.c
b/drivers/phy/int
Add definition for Ethernet PCS phy type.
Signed-off-by: Dilip Kota
Acked-by: Rob Herring
---
Changes on v9:
No Change
Changes on v8:
No Change
Changes on v7:
No Change
Changes on v6:
Add Acked-by: Rob Herring
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v9:
No Change
Changes on v8:
No Change.
Changes on v7:
No Change.
Changes on v6:
Add Reviewed
el.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/?h=phy-for-5.7
Dilip Kota (3):
dt-bindings: phy: Add PHY_TYPE_XPCS definition
dt-bindings: phy: Add YAML schemas for Intel ComboPhy
phy: intel: Add driver support for ComboPhy
.../devicetree/bindings/phy/intel,combo-phy.yaml | 101
d
ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: Dilip Kota
---
Changes on v9:
Add Acked-By: Vinod Koul
Fix compiler warning
drivers/phy/intel/phy-intel-combo.c:229:6: warning: cb_mode may be used
uninitialized in this function [-Wmaybe
On 5/19/2020 1:17 PM, Kishon Vijay Abraham I wrote:
Dilip,
On 5/19/2020 9:26 AM, Dilip Kota wrote:
On 5/18/2020 9:49 PM, Kishon Vijay Abraham I wrote:
Dilip,
On 5/15/2020 1:43 PM, Dilip Kota wrote:
This patch series adds Intel ComboPhy driver, respective yaml schemas
Changes on v8
On 5/18/2020 9:49 PM, Kishon Vijay Abraham I wrote:
Dilip,
On 5/15/2020 1:43 PM, Dilip Kota wrote:
This patch series adds Intel ComboPhy driver, respective yaml schemas
Changes on v8:
As per PHY Maintainer's request add description in comments for doing
register access through
Add definition for Ethernet PCS phy type.
Signed-off-by: Dilip Kota
Acked-by: Rob Herring
---
Changes on v8:
No Change
Changes on v7:
No Change
Changes on v6:
Add Acked-by: Rob Herring
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v8:
No Change.
Changes on v7:
No Change.
Changes on v6:
Add Reviewed-by: Rob Herring
ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: Dilip Kota
---
Changes on v8:
As per PHY Maintainer's request add description for doing register access
through regmap in comments.
Changes on v7:
Use device_node_to_regmap instead
fwnode_to_regmap() definition and use device_node_get_regmap()
Changes on v6:
Rebase patches on the latest maintainer's branch
https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/?h=phy-for-5.7
Dilip Kota (3):
dt-bindings: phy: Add PHY_TYPE_XPCS definition
dt-bindings: phy: Add
On 5/15/2020 3:39 PM, Vinod Koul wrote:
On 15-05-20, 12:30, Dilip Kota wrote:
ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: Dilip Kota
---
Changes on v8:
As per PHY Maintainer's request add description for doing register access
Add definition for Ethernet PCS phy type.
Signed-off-by: Dilip Kota
Acked-by: Rob Herring
---
Changes on v8:
No Change
Changes on v7:
No Change
Changes on v6:
Add Acked-by: Rob Herring
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v8:
No Change.
Changes on v7:
No Change.
Changes on v6:
Add Reviewed-by: Rob Herring
fwnode_to_regmap() definition and use device_node_get_regmap()
Changes on v6:
Rebase patches on the latest maintainer's branch
https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/?h=phy-for-5.7
Dilip Kota (3):
dt-bindings: phy: Add PHY_TYPE_XPCS definition
dt-bindings: phy: Add
ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: Dilip Kota
---
Changes on v8:
As per PHY Maintainer's request add description for doing register access
through regmap in comments.
Changes on v7:
Use device_node_to_regmap instead
Hi Vinod,
On 5/5/2020 3:54 PM, Dilip Kota wrote:
On 5/5/2020 1:21 PM, Vinod Koul wrote:
On 04-05-20, 17:32, Dilip Kota wrote:
On 5/4/2020 5:20 PM, Vinod Koul wrote:
On 04-05-20, 16:26, Dilip Kota wrote:
On 5/4/2020 3:29 PM, Vinod Koul wrote:
On 30-04-20, 15:15, Dilip Kota wrote
On 5/5/2020 7:23 PM, Mark Brown wrote:
On Mon, May 04, 2020 at 06:15:47PM +0800, Dilip Kota wrote:
On 4/29/2020 8:13 PM, Mark Brown wrote:
I just tried to get the history of removing workqueue in SPI driver, on
GRX500 (earlier chipset of LGM) the SPI transfers got timedout with
workqueues
On 5/5/2020 1:21 PM, Vinod Koul wrote:
On 04-05-20, 17:32, Dilip Kota wrote:
On 5/4/2020 5:20 PM, Vinod Koul wrote:
On 04-05-20, 16:26, Dilip Kota wrote:
On 5/4/2020 3:29 PM, Vinod Koul wrote:
On 30-04-20, 15:15, Dilip Kota wrote:
+ u32 mask, u32
On 4/29/2020 8:13 PM, Mark Brown wrote:
On Wed, Apr 29, 2020 at 04:20:53PM +0800, Dilip Kota wrote:
On 4/28/2020 7:10 PM, Daniel Schwierzeck wrote:
actually there is no real bottom half. Reading or writing the FIFOs is
fast and is therefore be done in hard IRQ context. But as the comment
On 5/4/2020 5:20 PM, Vinod Koul wrote:
On 04-05-20, 16:26, Dilip Kota wrote:
On 5/4/2020 3:29 PM, Vinod Koul wrote:
On 30-04-20, 15:15, Dilip Kota wrote:
+ u32 mask, u32 val)
+{
+ u32 reg_val;
+
+ reg_val = readl(base + reg
On 5/4/2020 3:29 PM, Vinod Koul wrote:
On 30-04-20, 15:15, Dilip Kota wrote:
+enum {
+ PHY_0,
+ PHY_1,
+ PHY_MAX_NUM
PHY_MAX_NUM = PHY_1?
Driver is using it for no. of PHYs/maximum PHY id.
Code snippets:
struct intel_combo_phy {
...
struct reset_control
On 4/30/2020 4:25 PM, Lee Jones wrote:
On Thu, 30 Apr 2020, Dilip Kota wrote:
This patch series adds Intel ComboPhy driver, respective yaml schemas
Changes on v7:
As per System control driver maintainer's inputs remove
fwnode_to_regmap() definition and use device_node_get_regmap
://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git/?h=phy-for-5.7
Dilip Kota (3):
dt-bindings: phy: Add PHY_TYPE_XPCS definition
dt-bindings: phy: Add YAML schemas for Intel ComboPhy
phy: intel: Add driver support for ComboPhy
.../devicetree/bindings/phy/intel,combo-phy.yaml | 101
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v7:
No Change.
Changes on v6:
Add Reviewed-by: Rob Herring
.../devicetree/bindings/phy/intel
ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: Dilip Kota
---
Changes on v7:
Use device_node_to_regmap instead of fwnode_to_regmap
Changes on v6:
No changes
Changes on v5:
Add changes as per inputs from Andy and Rob:
DT node uses
Add definition for Ethernet PCS phy type.
Signed-off-by: Dilip Kota
Acked-by: Rob Herring
---
Changes on v7:
No Change
Changes on v6:
Add Acked-by: Rob Herring
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy.h b/include/dt
On 4/28/2020 7:30 PM, Hauke Mehrtens wrote:
On 4/28/20 1:10 PM, Daniel Schwierzeck wrote:
Am 24.04.20 um 12:42 schrieb Dilip Kota:
...
Hi,
The Interrupt controller found on Danube till xrx300 which is probably
from Infineon like this SPI controller IP acknowledges the interrupts
also
On 4/28/2020 7:10 PM, Daniel Schwierzeck wrote:
Am 24.04.20 um 12:42 schrieb Dilip Kota:
Synchronize tx, rx and error interrupts by registering to the
same interrupt handler. Interrupt handler will recognize and process
the appropriate interrupt on the basis of interrupt status register
On 4/28/2020 6:00 PM, Mark Brown wrote:
On Tue, Apr 28, 2020 at 01:39:06PM +0800, Dilip Kota wrote:
Do you suggest to use different ISRs for multiple interrupt lines and single
ISR for single interrupt line? I see, this results in writing repetitive
code lines.
It looks like the shared case
On 4/28/2020 6:29 PM, Arnd Bergmann wrote:
On Tue, Apr 28, 2020 at 12:05 PM Lee Jones wrote:
On Tue, 21 Apr 2020, Dilip Kota wrote:
But, i feel return error for ACPI or oother, looks better because
'device_node' has fwnode pointer. And provide description
in the header file, mentioning
Hi Gustavo Pimentel,
On 10/21/2019 6:44 PM, Dilip Kota wrote:
Hi Gustavo Pimentel,
On 10/21/2019 4:29 PM, Gustavo Pimentel wrote:
Hi
On Mon, Oct 21, 2019 at 7:39:19, Dilip Kota
wrote:
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys
Hi Andrew Murray,
On 10/21/2019 7:19 PM, Andrew Murray wrote:
On Mon, Oct 21, 2019 at 02:39:18PM +0800, Dilip Kota wrote:
Add YAML shcemas for PCIe RC controller on Intel Gateway SoCs
s/shcemas/schemas/
which is Synopsys DesignWare based PCIe core.
The revision history below doesn't need
Hi Bjorn Helgaas,
On 10/22/2019 1:18 AM, Bjorn Helgaas wrote:
On Mon, Oct 21, 2019 at 02:38:50PM +0100, Andrew Murray wrote:
On Mon, Oct 21, 2019 at 02:39:20PM +0800, Dilip Kota wrote:
PCIe RC driver on Intel Gateway SoCs have a requirement
of changing link width and speed on the fly.
Please
Hi Andrew Murray,
On 10/21/2019 9:38 PM, Andrew Murray wrote:
On Mon, Oct 21, 2019 at 02:39:20PM +0800, Dilip Kota wrote:
PCIe RC driver on Intel Gateway SoCs have a requirement
of changing link width and speed on the fly.
So add the sysfs attributes to show and store the link
properties.
Add
Hi Bjorn Helgaas,
On 10/22/2019 1:17 AM, Bjorn Helgaas wrote:
On Mon, Oct 21, 2019 at 02:39:19PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare pci core.
Intel PCIe driver requires Upconfig support, fast
Hi Andrew Murray,
On 10/21/2019 9:03 PM, Andrew Murray wrote:
On Mon, Oct 21, 2019 at 02:39:19PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare pci core.
Intel PCIe driver requires Upconfig support, fast
Hi Gustavo Pimentel,
On 10/21/2019 4:29 PM, Gustavo Pimentel wrote:
Hi
On Mon, Oct 21, 2019 at 7:39:19, Dilip Kota
wrote:
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare pci core.
Intel PCIe driver requires Upconfig support, fast
Hi Gustavo Pimentel,
On 10/21/2019 4:40 PM, Gustavo Pimentel wrote:
On Mon, Oct 21, 2019 at 7:39:20, Dilip Kota
wrote:
PCIe RC driver on Intel Gateway SoCs have a requirement
of changing link width and speed on the fly.
So add the sysfs attributes to show and store the link
properties.
Add
Hi Gustavo Pimentel,
On 10/21/2019 4:08 PM, Gustavo Pimentel wrote:
Hi,
On Mon, Oct 21, 2019 at 7:39:17, Dilip Kota
wrote:
Intel PCIe is synopsys based controller utilizes the Designware
Please do this general replacement in all your patches.
s/synopsys/Synopsys
and
s/Designware
platform
specific interrupt configuration during core initialization. So
changed the subject line too.
Address v2 review comments for DT binding and PCIe driver
Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
dwc: PCI: intel: PCIe RC
configuration on the fly.
Signed-off-by: Dilip Kota
---
drivers/pci/controller/dwc/pcie-designware.c | 9 +++
drivers/pci/controller/dwc/pcie-designware.h | 3 +
drivers/pci/controller/dwc/pcie-intel-gw.c | 112 ++-
3 files changed, 123 insertions(+), 1 deletion(-)
diff
phy-names to 'pciephy'
Remove the dtsi node split of SoC and board in the example
Add #interrupt-cells = <1>; or else interrupt parsing will fail
Name yaml file with compatible name
Signed-off-by: Dilip Kota
---
.../devicetree/bindings/pci/intel-gw-pci
t;reset-assert-ms".
Remove unused APP logic Interrupt bit macro definitions.
Use dwc framework's dw_pcie_setup_rc() for PCIe host specific
configuration instead of redefining the same functionality in
the driver.
Move the whole DT parsing specific code t
Hi Philipp,
On 10/8/2019 11:56 PM, Philipp Zabel wrote:
Hi Martin,
On Mon, 2019-10-07 at 21:53 +0200, Martin Blumenstingl wrote:
Hi Philipp,
On Thu, Oct 3, 2019 at 4:19 PM Philipp Zabel wrote:
[...]
because the register layout was greatly simplified for the newer SoCs
(for which there is
Hi Martin,Philipp,
On 10/8/2019 3:53 AM, Martin Blumenstingl wrote:
Hi Philipp,
On Thu, Oct 3, 2019 at 4:19 PM Philipp Zabel wrote:
[...]
because the register layout was greatly simplified for the newer SoCs
(for which there is reset-intel) compared to the older ones
(reset-lantiq).
Dilip's
Hi Martin and Philipp,
On 20/9/2019 10:47 AM, Dilip Kota wrote:
Hi Martin,
On 9/20/2019 3:51 AM, Martin Blumenstingl wrote:
Hi Dilip,
(sorry for the late reply)
On Thu, Sep 12, 2019 at 8:38 AM Dilip Kota
wrote:
[...]
The major difference between the vrx200 and lgm is:
1.) RCU in vrx200
Hi Rob,
On 18/9/2019 2:56 PM, Dilip Kota wrote:
On 9/18/2019 2:40 AM, Rob Herring wrote:
On Wed, Sep 04, 2019 at 06:10:30PM +0800, Dilip Kota wrote:
The Intel PCIe RC controller is Synopsys Designware
based PCIe core. Add YAML schemas for PCIe in RC mode
present in Intel Universal Gateway
Hi Martin,
On 9/20/2019 3:51 AM, Martin Blumenstingl wrote:
Hi Dilip,
(sorry for the late reply)
On Thu, Sep 12, 2019 at 8:38 AM Dilip Kota wrote:
[...]
The major difference between the vrx200 and lgm is:
1.) RCU in vrx200 is having multiple register regions wheres RCU in lgm
has one single
Hi Thomas,
On 9/19/2019 4:36 PM, Langer, Thomas wrote:
Hi Dilip,
-Original Message-
From: devicetree-ow...@vger.kernel.org On Behalf Of Dilip Kota
Sent: Donnerstag, 19. September 2019 10:06
To: Martin Blumenstingl
Cc: Chuan Hua, Lei ; Kim, Cheol Yong
; devicet...@vger.kernel.org
Hi Martin,
On 9/12/2019 2:38 PM, Dilip Kota wrote:
Re-sending the mail, because of delivery failure.
sorry for the spam.
Hi Martin,
On 9/6/2019 4:53 AM, Martin Blumenstingl wrote:
Hi,
On Thu, Sep 5, 2019 at 4:38 AM Chuan Hua, Lei
wrote:
[...]
I'm not surprised that we got some of the IP
On 9/18/2019 2:40 AM, Rob Herring wrote:
On Wed, Sep 04, 2019 at 06:10:30PM +0800, Dilip Kota wrote:
The Intel PCIe RC controller is Synopsys Designware
based PCIe core. Add YAML schemas for PCIe in RC mode
present in Intel Universal Gateway soc.
Signed-off-by: Dilip Kota
---
changes on v3
Hi Rob,
On 9/18/2019 2:33 AM, Rob Herring wrote:
On Fri, Sep 06, 2019 at 12:19:50PM +0300, Andy Shevchenko wrote:
On Thu, Sep 05, 2019 at 10:31:29PM +0200, Martin Blumenstingl wrote:
On Wed, Sep 4, 2019 at 12:11 PM Dilip Kota wrote:
+ phy-names:
+const: pciephy
the most popular choice
On 9/13/2019 6:12 PM, andriy.shevche...@intel.com wrote:
On Fri, Sep 13, 2019 at 05:20:26PM +0800, Dilip Kota wrote:
On 9/12/2019 6:49 PM, Gustavo Pimentel wrote:
On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
wrote:
Hi, I just return from parental leave, therefore I still trying to get
On 9/12/2019 6:49 PM, Gustavo Pimentel wrote:
On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
wrote:
Quoting Andrew Murray:
Quoting Gustavo Pimentel:
On 9/12/2019 4:25 PM, Andrew Murray wrote:
[...]
+static void intel_pcie_max_link_width_setup(struct intel_pcie_port *lpp)
+{
+ u32
Quoting Andrew Murray:
Quoting Gustavo Pimentel:
On 9/12/2019 4:25 PM, Andrew Murray wrote:
[...]
+static void intel_pcie_max_link_width_setup(struct intel_pcie_port *lpp)
+{
+ u32 mask, val;
+
+ /* HW auto bandwidth negotiation must be enabled */
+ pcie_rc_cfg_wr_mask(lpp,
Hi Andy,
On 9/5/2019 7:40 PM, Andy Shevchenko wrote:
On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci
Hi Andrew Murray,
On 9/11/2019 6:30 PM, Andrew Murray wrote:
On Tue, Sep 10, 2019 at 03:46:17PM +0800, Dilip Kota wrote:
Hi Andrew Murray,
Please find my response inline.
On 9/9/2019 4:31 PM, Andrew Murray wrote:
On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
On 9/6/2019 7:20
Re-sending the mail, because of delivery failure.
sorry for the spam.
Hi Martin,
On 9/6/2019 4:53 AM, Martin Blumenstingl wrote:
Hi,
On Thu, Sep 5, 2019 at 4:38 AM Chuan Hua, Lei
wrote:
[...]
I'm not surprised that we got some of the IP block layout for the
VRX200 RCU "wrong" - all
[Got delivery failure mail; so re-sending the mail]
Hi Andrew Murray,
Please find my response inline.
On 9/9/2019 4:31 PM, Andrew Murray wrote:
On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
On 9/6/2019 7:20 PM, Andrew Murray wrote:
On Fri, Sep 06, 2019 at 06:58:11PM +0800
On 9/6/2019 5:19 PM, Andy Shevchenko wrote:
On Thu, Sep 05, 2019 at 10:31:29PM +0200, Martin Blumenstingl wrote:
On Wed, Sep 4, 2019 at 12:11 PM Dilip Kota wrote:
+ phy-names:
+const: pciephy
the most popular choice in Documentation/devicetree/bindings/pci/ is "pcie-phy&qu
On 9/6/2019 7:20 PM, Andrew Murray wrote:
On Fri, Sep 06, 2019 at 06:58:11PM +0800, Dilip Kota wrote:
Hi Andrew Murray,
Thanks for the review. Please find my response inline.
On 9/5/2019 6:45 PM, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support
Hi Andrew Murray,
Thanks for the review. Please find my response inline.
On 9/5/2019 6:45 PM, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci
Hi Andy,
Thanks for the review comments, please find my response inline.
On 9/4/2019 9:05 PM, Andy Shevchenko wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware
Hi Chuan Hua,
On 9/5/2019 10:23 AM, Chuan Hua, Lei wrote:
Hi Dilip,
On 9/4/2019 6:10 PM, Dilip Kota wrote:
The Intel PCIe RC controller is Synopsys Designware
based PCIe core. Add YAML schemas for PCIe in RC mode
present in Intel Universal Gateway soc.
Signed-off-by: Dilip Kota
---
changes
The Intel PCIe RC controller is Synopsys Designware
based PCIe core. Add YAML schemas for PCIe in RC mode
present in Intel Universal Gateway soc.
Signed-off-by: Dilip Kota
---
changes on v3:
Add the appropriate License-Identifier
Rename intel,rst-interval to 'reset-assert-us
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci core.
Signed-off-by: Dilip Kota
---
changes on v3:
Rename PCIe app logic registers with PCIE_APP prefix.
PCIE_IOP_CTRL configuration is not required. Remove
driver does platform
specific interrupt configuration during core initialization. So
changed the subject line too.
Address v2 review comments for DT binding and PCIe driver
Dilip Kota (2):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
dwc: PCI
Hi Rob,
On 8/27/2019 10:04 PM, Dilip Kota wrote:
Hi Rob,
On 8/26/2019 7:23 PM, Rob Herring wrote:
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota
wrote:
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota
wrote:
Add YAML schemas for the reset
Hi Rob,
On 8/26/2019 7:23 PM, Rob Herring wrote:
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota wrote:
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed
On 8/27/2019 4:14 AM, Martin Blumenstingl wrote:
second example: pcie-tegra194 (only in -next, will be part of v5.4)
struct tegra_pcie_dw {
...
struct dw_pcie pci;
...
};
so some drivers store a pointer pointer to the dw_pcie struct vs.
embedding the dw_pcie struct
Hi Martin,
On 8/27/2019 11:09 AM, Chuan Hua, Lei wrote:
[...]
now I am wondering:
- if we don't have to disable the interrupt line (once it is enabled),
why can't we enable all of these interrupts at initialization time
(instead of doing it on-demand)?
Good point! we even can remote map_irq
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota
---
Changes on v2:
Address review comments
Update the compatible
On 8/23/2019 6:09 PM, Philipp Zabel wrote:
On Fri, 2019-08-23 at 17:47 +0800, Dilip Kota wrote:
[...]
Thanks for pointing it out.
Reset is not supported on LGM platform.
I will update the reset_device() definition to "return -EOPNOTSUPP"
In that case you can just drop intel_re
[Got delivery failure mail , so re-sending the mail]
Hi Martin,
Thanks for review comments, please find my response inline.
On 8/26/2019 11:30 AM, Chuan Hua, Lei wrote:
Hi Martin,
Thanks for your valuable comments. I reply some of them as below.
Regards,
Chuanhua
On 8/25/2019 5:03 AM,
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