Thierry Reding writes:
> diff --git a/include/dt-bindings/memory/tegra124-mc.h
> b/include/dt-bindings/memory/tegra124-mc.h
> new file mode 100644
> index ..6b1617ce022f
> --- /dev/null
> +++ b/include/dt-bindings/memory/tegra124-mc.h
> @@ -0,0 +1,30 @@
> +#ifndef
Thierry Reding thierry.red...@gmail.com writes:
diff --git a/include/dt-bindings/memory/tegra124-mc.h
b/include/dt-bindings/memory/tegra124-mc.h
new file mode 100644
index ..6b1617ce022f
--- /dev/null
+++ b/include/dt-bindings/memory/tegra124-mc.h
@@ -0,0 +1,30 @@
+#ifndef
Thierry Reding writes:
> From: Thierry Reding
>
> The memory controller on NVIDIA Tegra124 exposes various knobs that can
> be used to tune the behaviour of the clients attached to it.
>
> Currently this driver sets up the latency allowance registers to the HW
> defaults. Eventually an API
Thierry Reding writes:
> From: Thierry Reding
>
> When an IOMMU device is available on the platform bus, allocate an IOMMU
> domain and attach the display controllers to it. The display controllers
> can then scan out non-contiguous buffers by mapping them through the
> IOMMU.
>
>
Thierry Reding writes:
> From: Thierry Reding
>
> Attach to the device's master interface of the IOMMU at .probe() time.
> IOMMU support becomes available via the DMA mapping API interoperation
> code, but this explicit attachment is necessary to ensure proper probe
> order.
>
> Signed-off-by:
Thierry Reding thierry.red...@gmail.com writes:
From: Thierry Reding tred...@nvidia.com
When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them
Thierry Reding thierry.red...@gmail.com writes:
From: Thierry Reding tred...@nvidia.com
Attach to the device's master interface of the IOMMU at .probe() time.
IOMMU support becomes available via the DMA mapping API interoperation
code, but this explicit attachment is necessary to ensure
Thierry Reding thierry.red...@gmail.com writes:
From: Thierry Reding tred...@nvidia.com
The memory controller on NVIDIA Tegra124 exposes various knobs that can
be used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the
Arnd Bergmann writes:
>> > +Multiple-master IOMMU:
>> > +--
>> > +
>> > + iommu {
>> > + /* the specifier represents the ID of the master */
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + };
>> > +
>> > +
Arnd Bergmann a...@arndb.de writes:
+Multiple-master IOMMU:
+--
+
+ iommu {
+ /* the specifier represents the ID of the master */
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ master {
+
Hiroshi Doyu wrote @ Thu, 12 Dec 2013 14:14:04 +0200 (EET):
> > > From 8f7c0404aa68f0e8dbe0babc240590f6528ecc1f Mon Sep 17 00:00:00 2001
> > > From: Hiroshi Doyu
> > > Date: Fri, 15 Nov 2013 10:52:53 +0200
> > > Subject: [PATCH] of: introduce of
Thierry Reding wrote @ Sat, 14 Dec 2013 13:24:22
+0100:
> * PGP Signed by an unknown key
>
> On Thu, Dec 12, 2013 at 06:14:02PM -0800, Greg KH wrote:
> > On Thu, Dec 12, 2013 at 11:39:20AM +, Grant Likely wrote:
> > > On Thu, 12 Dec 2013 09:57:05 +0200, Hiroshi Do
Thierry Reding thierry.red...@gmail.com wrote @ Sat, 14 Dec 2013 13:24:22
+0100:
* PGP Signed by an unknown key
On Thu, Dec 12, 2013 at 06:14:02PM -0800, Greg KH wrote:
On Thu, Dec 12, 2013 at 11:39:20AM +, Grant Likely wrote:
On Thu, 12 Dec 2013 09:57:05 +0200, Hiroshi Doyu hd
Hiroshi Doyu hd...@nvidia.com wrote @ Thu, 12 Dec 2013 14:14:04 +0200 (EET):
From 8f7c0404aa68f0e8dbe0babc240590f6528ecc1f Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu hd...@nvidia.com
Date: Fri, 15 Nov 2013 10:52:53 +0200
Subject: [PATCH] of: introduce
Grant Likely wrote @ Thu, 12 Dec 2013 12:34:17 +0100:
> On Wed, 11 Dec 2013 14:33:38 +0100, Hiroshi Doyu wrote:
> > Hi Grant,
> >
> > Grant Likely wrote @ Wed, 11 Dec 2013 14:28:45
> > +0100:
> >
> > > On Thu, 21 Nov 2013 11:57:00 -0700, Stephen Warr
be still deferred via probe().
Signed-off-by: Hiroshi Doyu
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu
---
drivers/iommu/iommu.c | 13 +++--
include/linux/iommu.h | 4
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
inde
mmu device is
populated.
Signed-off-by: Hiroshi Doyu
---
v6:
Spinned off only of_iommu part from:
[PATCHv5 2/9] driver/core: populate devices in order for IOMMUs
v5:
Use "iommus=" binding instread of arm,smmu's "#stream-id-cells".
v4:
This is newly added, and the successo
-by: Hiroshi Doyu
Cc: Joerg Roedel
Cc: Thierry Reding
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu
---
drivers/iommu/of_iommu.c | 37 +
include/linux/of_iommu.h | 16
2 files changed, 53 insertions(+)
diff --git a/drivers/iommu/of_iommu.c b
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu
---
v6:
- Explained "#iommu-cells" in the binding documen
, the traditional devices(SD/MMC, USB) wouldn't
be affected, and the system could continue most likely. DMA API(ARM)
needs ARM_DMA_USE_IOMMU to be enabled.
Signed-off-by: Hiroshi Doyu
---
v6:
Use smmu_iommu_{bound,unbind}_driver() instead of
smmu_iommu_{add,del}_device() to register devices to SMMU.
v5
Signed-off-by: Hiroshi Doyu
---
include/dt-bindings/memory/tegra-swgroup.h | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 include/dt-bindings/memory/tegra-swgroup.h
diff --git a/include/dt-bindings/memory/tegra-swgroup.h
b/include/dt-bindings/memory/tegra
mmu device is populated. Then,
those deferred iommu master devices are populated and configured with
help of the already populated iommu device.
Signed-off-by: Hiroshi Doyu
Cc: Greg Kroah-Hartman
---
This is related to the following discussion:
[RFC PATCH] Documentation: devicetree: add description for g
This allows to inquire if SMMU is populated or not.
Suggested by Thierry Reding and copied his example code.
Signed-off-by: Hiroshi Doyu
Cc: Thierry Reding
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu
---
drivers/iommu/tegra-smmu.c | 55 +-
1
" so that
"swgroup's'" is used here. This "swgroups" is the term used in Tegra
TRM. Rename along with TRM.
Signed-off-by: Hiroshi Doyu
---
v4:
New for v4
Signed-off-by: Hiroshi Doyu
---
drivers/iommu/tegra-smmu.c | 36 ++--
1 file changed, 18 inse
;
Now SWGROUP ID is the global HardWare Accelerator(HWA) identifier
among all Tegra SoC except Tegra2.
Signed-off-by: Hiroshi Doyu
---
v5:
Added SMMU_ASID_BASE(== SMMU_AFI_ASID).
Removed unused ASID offset definitions.
Use 'unsigned long *' instead of u64 for swgroups bitmap.
v4:
Combined
The device, which belongs to the same ASID, can try to enable the same
ASID as the other swgroup devices. This should be allowed but just
skip the actual register write. If the write value is different, it
will return -EINVAL.
Signed-off-by: Hiroshi Doyu
---
v4:
This was the part of v3, which
= MC_SMMU_AFI_ASID_0 + ID * 4;
Now SWGROUP ID is the global HardWare Accelerator(HWA) identifier
among all Tegra SoC except Tegra2.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v5:
Added SMMU_ASID_BASE(== SMMU_AFI_ASID).
Removed unused ASID offset definitions.
Use 'unsigned long *' instead of u64 for swgroups
.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
Use 0x instead of ~0UL since dtc expand this to ~0ULL.
v5:
Added new macro TEGRA_SWGROUP_CELLS() and WO_U32_OF_U64().
v4:
This is almost same as the previous v3. Just TEGRA_SWGROUP_MAX is
added.
[PATCHv3 15/19] ARM: tegra: Create a DT
. Then,
those deferred iommu master devices are populated and configured with
help of the already populated iommu device.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
This is related to the following discussion:
[RFC PATCH] Documentation
The device, which belongs to the same ASID, can try to enable the same
ASID as the other swgroup devices. This should be allowed but just
skip the actual register write. If the write value is different, it
will return -EINVAL.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v4:
This was the part
This allows to inquire if SMMU is populated or not.
Suggested by Thierry Reding and copied his example code.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
Cc: Thierry Reding thierry.red...@gmail.com
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/iommu/tegra-smmu.c
is the term used in Tegra
TRM. Rename along with TRM.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v4:
New for v4
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/iommu/tegra-smmu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
- Explained #iommu-cells in the binding
, the traditional devices(SD/MMC, USB) wouldn't
be affected, and the system could continue most likely. DMA API(ARM)
needs ARM_DMA_USE_IOMMU to be enabled.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
Use smmu_iommu_{bound,unbind}_driver() instead of
smmu_iommu_{add,del}_device() to register
is
populated.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
Spinned off only of_iommu part from:
[PATCHv5 2/9] driver/core: populate devices in order for IOMMUs
v5:
Use iommus= binding instread of arm,smmu's #stream-id-cells.
v4:
This is newly added, and the successor of the following RFC
-by: Hiroshi Doyu hd...@nvidia.com
Cc: Joerg Roedel j...@8bytes.org
Cc: Thierry Reding thierry.red...@gmail.com
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/iommu/of_iommu.c | 37 +
include/linux/of_iommu.h | 16
2
via probe().
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
New for v6.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/iommu/iommu.c | 13 +++--
include/linux/iommu.h | 4
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/iommu.c b
Grant Likely grant.lik...@linaro.org wrote @ Thu, 12 Dec 2013 12:34:17 +0100:
On Wed, 11 Dec 2013 14:33:38 +0100, Hiroshi Doyu hd...@nvidia.com wrote:
Hi Grant,
Grant Likely grant.lik...@linaro.org wrote @ Wed, 11 Dec 2013 14:28:45
+0100:
On Thu, 21 Nov 2013 11:57:00 -0700, Stephen
Iterating over a property containing a list of phandles with arguments
is a common operation for device drivers. This patch adds a new
of_property_for_each_phandle_with_args() macro to make the iteration
simpler.
Signed-off-by: Hiroshi Doyu
Cc: Rob Herring
Cc: Grant Likely
---
v7:
Fixed some
il/linux-arm-kernel/2013-July/181888.html
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/180267.html
Available in the git repository at:
git://g...@nv-tegra.nvidia.com/user/hdoyu/linux.git smmu-upstreaming@20131212
Hiroshi Doyu (12):
of: introduce of_property_for_each_phandle_wi
Hi Grant,
Grant Likely wrote @ Wed, 11 Dec 2013 14:28:45 +0100:
> On Thu, 21 Nov 2013 11:57:00 -0700, Stephen Warren
> wrote:
> > On 11/21/2013 10:17 AM, Hiroshi Doyu wrote:
> > > Iterating over a property containing a list of phandles with arguments
> > > is
Hi Grant,
Grant Likely grant.lik...@linaro.org wrote @ Wed, 11 Dec 2013 14:28:45 +0100:
On Thu, 21 Nov 2013 11:57:00 -0700, Stephen Warren swar...@wwwdotorg.org
wrote:
On 11/21/2013 10:17 AM, Hiroshi Doyu wrote:
Iterating over a property containing a list of phandles with arguments
://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/180267.html
Available in the git repository at:
git://g...@nv-tegra.nvidia.com/user/hdoyu/linux.git smmu-upstreaming@20131212
Hiroshi Doyu (12):
of: introduce of_property_for_each_phandle_with_args()
iommu/of: introduce a global iommu device list
Iterating over a property containing a list of phandles with arguments
is a common operation for device drivers. This patch adds a new
of_property_for_each_phandle_with_args() macro to make the iteration
simpler.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
Cc: Rob Herring robherri...@gmail.com
On Mon, 25 Nov 2013 14:49:37 +0100
Hiroshi Doyu wrote:
> Hi Joerg,
>
> Do you have some time to review this patch along with the following ones?
>
> [PATCHv6 02/13] iommu/of: introduce a global iommu device list
> http://lists.linuxfoundation.org/pipermail/iommu/2013-No
On Mon, 25 Nov 2013 14:49:37 +0100
Hiroshi Doyu hd...@nvidia.com wrote:
Hi Joerg,
Do you have some time to review this patch along with the following ones?
[PATCHv6 02/13] iommu/of: introduce a global iommu device list
http://lists.linuxfoundation.org/pipermail/iommu/2013-November
On Mon, 2 Dec 2013 15:39:25 +0100
Rob Herring wrote:
> On Mon, Dec 2, 2013 at 5:02 AM, Hiroshi Doyu wrote:
> > Stephen Warren wrote @ Sun, 1 Dec 2013 20:00:09
> > +0100:
> >
> >> On 11/29/2013 04:46 AM, Hiroshi Doyu wrote:
> >> ...
> >&g
Stephen Warren wrote @ Sun, 1 Dec 2013 20:00:09 +0100:
> On 11/29/2013 04:46 AM, Hiroshi Doyu wrote:
> ...
> > Iterating over a property containing a list of phandles with arguments
> > is a common operation for device drivers. This patch adds a new
> > of_property_fo
Stephen Warren swar...@wwwdotorg.org wrote @ Sun, 1 Dec 2013 20:00:09 +0100:
On 11/29/2013 04:46 AM, Hiroshi Doyu wrote:
...
Iterating over a property containing a list of phandles with arguments
is a common operation for device drivers. This patch adds a new
On Mon, 2 Dec 2013 15:39:25 +0100
Rob Herring robherri...@gmail.com wrote:
On Mon, Dec 2, 2013 at 5:02 AM, Hiroshi Doyu hd...@nvidia.com wrote:
Stephen Warren swar...@wwwdotorg.org wrote @ Sun, 1 Dec 2013 20:00:09
+0100:
On 11/29/2013 04:46 AM, Hiroshi Doyu wrote:
...
Iterating
Hiroshi Doyu wrote @ Thu, 28 Nov 2013 14:58:18 +0200 (EET):
> > In other words, an implementation more along the lines of
> > include/linux/of.h's:
> >
> > #define of_property_for_each_u32(np, propname, prop, p, u) \
> > for (prop = of_fi
Hiroshi Doyu hd...@nvidia.com wrote @ Thu, 28 Nov 2013 14:58:18 +0200 (EET):
In other words, an implementation more along the lines of
include/linux/of.h's:
#define of_property_for_each_u32(np, propname, prop, p, u) \
for (prop = of_find_property(np, propname, NULL
Stephen Warren wrote @ Thu, 21 Nov 2013 19:57:00 +0100:
> On 11/21/2013 10:17 AM, Hiroshi Doyu wrote:
> > Iterating over a property containing a list of phandles with arguments
> > is a common operation for device drivers. This patch adds a new
> > of_property_for_each_phan
Stephen Warren swar...@wwwdotorg.org wrote @ Thu, 21 Nov 2013 19:57:00 +0100:
On 11/21/2013 10:17 AM, Hiroshi Doyu wrote:
Iterating over a property containing a list of phandles with arguments
is a common operation for device drivers. This patch adds a new
2013 14:40:41 +0100
Hiroshi Doyu wrote:
> ops->{bound,unbind}_driver() functions are called at
> BUS_NOTIFY_{BOUND,UNBIND}_DRIVER respectively.
>
> This is necessary to control the device population order. IOMMU master
> devices depend on an IOMMU device instanciation. IOMMU ma
2013 14:40:41 +0100
Hiroshi Doyu hd...@nvidia.com wrote:
ops-{bound,unbind}_driver() functions are called at
BUS_NOTIFY_{BOUND,UNBIND}_DRIVER respectively.
This is necessary to control the device population order. IOMMU master
devices depend on an IOMMU device instanciation. IOMMU master
Thierry Reding wrote @ Wed, 20 Nov 2013 14:14:48
+0100:
> > Does the above mean the following?
> >
> > int of_iommu_attach(struct device *dev)
> > {
> > int i;
> > struct of_phandle_args args;
> >
> > of_property_for_each_phandle_with_args(dev->of_node, "iommus",
> >
Thierry Reding thierry.red...@gmail.com wrote @ Wed, 20 Nov 2013 14:14:48
+0100:
Does the above mean the following?
int of_iommu_attach(struct device *dev)
{
int i;
struct of_phandle_args args;
of_property_for_each_phandle_with_args(dev-of_node, iommus,
> length.
> > >
> > > Signed-off-by: Antti P Miettinen
> > > Reviewed-by: Hiroshi Doyu
> > > Tested-by: Hiroshi Doyu
> >
> > When fixing a bug, please provide a description of the user-visible
> > impact of that bug. This is so that others
Stephen Warren wrote @ Tue, 19 Nov 2013 22:22:47 +0100:
> On 11/19/2013 05:03 AM, Hiroshi Doyu wrote:
> > Hi Thierry,
> >
> > Thierry Reding wrote @ Tue, 19 Nov 2013 11:25:07
> > +0100:
> >
> >> From earlier discussions I thought the goal was t
The device, which belongs to the same ASID, can try to enable the same
ASID as the other swgroup devices. This should be allowed but just
skip the actual register write. If the write value is different, it
will return -EINVAL.
Signed-off-by: Hiroshi Doyu
---
v4:
This was the part of v3, which
" so that
"swgroup's'" is used here. This "swgroups" is the term used in Tegra
TRM. Rename along with TRM.
Signed-off-by: Hiroshi Doyu
---
v4:
New for v4
---
drivers/iommu/tegra-smmu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
d
to be used by both
device tree files, and drivers implementing this binding, which
guarantees that the two stay in sync. This also makes device trees
more readable by using names instead of magic numbers. For HOTRESET
bit shifting we need another conversion table, which will come later.
Signed-off-b
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu
---
v5:
"iommu=" in a device DT is used instead of &q
ed on Thierry Reding's and Stephen Warren's feedback
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/181888.html
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/180267.html
Available in the git repository at:
git://g...@nv-tegra.nvidia.com/user/
, the traditional devices(SD/MMC, USB) wouldn't
be affected, and the system could continue most likely. DMA API(ARM)
needs ARM_DMA_USE_IOMMU to be enabled.
Signed-off-by: Hiroshi Doyu
---
v5:
Add check NUM_OF_STATIC_MAPS < #asids.
v4:
Combined the following from v3. This makes more sense what they
The following pattern of code is tempting:
for (i = 0; !of_parse_phandle_with_args(np, list, cells, i, args); i++)
Signed-off-by: Hiroshi Doyu
---
v5:
New patch for v5.
---
include/linux/of.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/of.h b/include/linux/of.h
index
The following pattern of code is tempting:
for (i = 0; !of_parse_phandle_with_args(np, list, cells, i, args); i++)
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v5:
New patch for v5.
---
include/linux/of.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/of.h b/include
, the traditional devices(SD/MMC, USB) wouldn't
be affected, and the system could continue most likely. DMA API(ARM)
needs ARM_DMA_USE_IOMMU to be enabled.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v5:
Add check NUM_OF_STATIC_MAPS #asids.
v4:
Combined the following from v3. This makes more sense
://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/181888.html
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/180267.html
Available in the git repository at:
git://g...@nv-tegra.nvidia.com/user/hdoyu/linux.git smmu-upstreaming@20131119
Hiroshi Doyu (9):
of: introduce
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v5:
iommu= in a device DT is used instead of mmu
.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v5:
Added new macro TEGRA_SWGROUP_CELLS() and WO_U32_OF_U64().
v4:
This is almost same as the previous v3. Just TEGRA_SWGROUP_MAX is
added.
[PATCHv3 15/19] ARM: tegra: Create a DT header defining SWGROUP ID
---
include/dt-bindings/memory/tegra
is the term used in Tegra
TRM. Rename along with TRM.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v4:
New for v4
---
drivers/iommu/tegra-smmu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu
The device, which belongs to the same ASID, can try to enable the same
ASID as the other swgroup devices. This should be allowed but just
skip the actual register write. If the write value is different, it
will return -EINVAL.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v4:
This was the part
Stephen Warren swar...@wwwdotorg.org wrote @ Tue, 19 Nov 2013 22:22:47 +0100:
On 11/19/2013 05:03 AM, Hiroshi Doyu wrote:
Hi Thierry,
Thierry Reding thierry.red...@gmail.com wrote @ Tue, 19 Nov 2013 11:25:07
+0100:
From earlier discussions I thought the goal was to actually defer
.
Signed-off-by: Antti P Miettinen amietti...@nvidia.com
Reviewed-by: Hiroshi Doyu hd...@nvidia.com
Tested-by: Hiroshi Doyu hd...@nvidia.com
When fixing a bug, please provide a description of the user-visible
impact of that bug. This is so that others can decide which kernel
dma_alloc_coherent wants to split pages after allocation in order to
reduce the memory footprint. This does not work well with GFP_COMP
pages, so drop this flag before allocation.
Signed-off-by: Hiroshi Doyu
---
arch/arm/mm/dma-mapping.c | 7 +++
1 file changed, 7 insertions
dma_alloc_coherent wants to split pages after allocation in order to
reduce the memory footprint. This does not work well with GFP_COMP
pages, so drop this flag before allocation.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/mm/dma-mapping.c | 7 +++
1 file changed, 7
YoungJun Cho wrote @ Mon, 17 Jun 2013 06:18:52 +0200:
> In __iommu_get_pages(), the cpu_addr is checked wheather in
> atomic_pool range or not. So if the cpu_addr is in atomic_pool
> range, it does not need to check twice.
>
> Signed-off-by: YoungJun Cho
> Signed-off-by: Kyungmin Park
Looks
YoungJun Cho yj44@samsung.com wrote @ Mon, 17 Jun 2013 06:18:52 +0200:
In __iommu_get_pages(), the cpu_addr is checked wheather in
atomic_pool range or not. So if the cpu_addr is in atomic_pool
range, it does not need to check twice.
Signed-off-by: YoungJun Cho yj44@samsung.com
Stephen Warren wrote @ Fri, 15 Mar 2013 06:23:38 +0100:
> On 03/14/2013 03:08 AM, Hiroshi Doyu wrote:
> > Make this depend on CONFIG_PM. This protection is necessary to not
> > cause any build errors with any combination of PM features especially
> > when supporting a
Stephen Warren swar...@wwwdotorg.org wrote @ Fri, 15 Mar 2013 06:23:38 +0100:
On 03/14/2013 03:08 AM, Hiroshi Doyu wrote:
Make this depend on CONFIG_PM. This protection is necessary to not
cause any build errors with any combination of PM features especially
when supporting a new SoC where
Make this depend on CONFIG_PM.
Signed-off-by: Hiroshi Doyu
---
drivers/memory/tegra30-mc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c
index 0b97598..f4ae074 100644
--- a/drivers/memory/tegra30-mc.c
+++ b/drivers/memory/tegra30
Make this depend on CONFIG_PM. This protection is necessary to not
cause any build errors with any combination of PM features especially
when supporting a new SoC where each PM features are being enabled
one-by-one during its depelopment.
Signed-off-by: Hiroshi Doyu
Reported-by: Joseph Lo
Make this depend on CONFIG_PM. This protection is necessary to not
cause any build errors with any combination of PM features especially
when supporting a new SoC where each PM features are being enabled
one-by-one during its depelopment.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
Reported
Make this depend on CONFIG_PM.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/memory/tegra30-mc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c
index 0b97598..f4ae074 100644
--- a/drivers/memory/tegra30-mc.c
+++ b
On Fri, 22 Feb 2013 16:02:28 +0100
Peter De Schrijver wrote:
> Add a table lookup feature to the mux clock. Also allow arbitrary masks
> instead of the width. This will be used by some clocks on Tegra114.
>
> Signed-off-by: Peter De Schrijver
> @@ -42,7 +43,17 @@ static u8
On Fri, 22 Feb 2013 16:02:28 +0100
Peter De Schrijver pdeschrij...@nvidia.com wrote:
Add a table lookup feature to the mux clock. Also allow arbitrary masks
instead of the width. This will be used by some clocks on Tegra114.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
@@
To avoid the duplication of CLK ID defines both in boot/dts and kernel
source, use the one from the DT header file and get rid of own
definitions in kernel source.
Signed-off-by: Hiroshi Doyu
---
drivers/clk/tegra/clk-tegra20.c | 307 ++-
1 file changed, 145
:
+ #include
Signed-off-by: Hiroshi Doyu
---
Makefile |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 0b4bf62..7f54cdb 100644
--- a/Makefile
+++ b/Makefile
@@ -364,7 +364,7 @@ LINUXINCLUDE:= \
-I$(srctree)/arch/$(hdr-arch)/include
Replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
.../bindings/clock/nvidia,tegra114-car.txt | 261 +---
arch/arm/boot/dts/tegra114.dtsip
To replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
arch/arm/boot/dts/tegra114-car.h | 272 ++
1 file changed, 272 insertions(+)
create mode 100
Replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
.../bindings/clock/nvidia,tegra30-car.txt | 207 +---
arch/arm/boot/dts/tegra30.dtsip
To replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
arch/arm/boot/dts/tegra30-car.h | 218 +++
1 file changed, 218 insertions(+)
create mode 100
Replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
.../bindings/clock/nvidia,tegra20-car.txt | 150 +---
arch/arm/boot/dts/tegra20-paz00.dtsp |
To replace magic number in tegra_car:
- clocks = <_car 28>;
+ clocks = <_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu
---
arch/arm/boot/dts/tegra20-car.h | 158 +++
1 file changed, 158 insertions(+)
create mode 100
://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149672.html
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149804.html
Hiroshi Doyu (6):
ARM: tegra20: create a DT header defining CLK IDs
ARM: tegra20: convert device tree files to use CLK defines
ARM: tegra30
://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149672.html
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149804.html
Hiroshi Doyu (6):
ARM: tegra20: create a DT header defining CLK IDs
ARM: tegra20: convert device tree files to use CLK defines
ARM: tegra30
To replace magic number in tegra_car:
- clocks = tegra_car 28;
+ clocks = tegra_car CLK_HOST1X;
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/tegra20-car.h | 158 +++
1 file changed, 158 insertions(+)
create
To replace magic number in tegra_car:
- clocks = tegra_car 28;
+ clocks = tegra_car CLK_HOST1X;
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/tegra30-car.h | 218 +++
1 file changed, 218 insertions(+)
create
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