[PATCH v2 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman <meg...@megous.com> Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng <

[PATCH v2 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- Changes in v2: - Added

[PATCH v2 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

unction name] Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Added Chen-Yu's Review tag. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/b

[PATCH v2 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

From: Ondrej Jirman H3/H5 SoCs contain an I2C controller optionally available on the PL0 and PL1 pins. This patch adds pinmux configuration for this controller. Signed-off-by: Ondrej Jirman [Icenowy: change commit message, node name and function name] Signed-off-by: Icenowy Zheng Reviewed

[PATCH v2 02/10] regulator: add support for SY8106A regulator

nowy: Change commit message, remove enable/disable code, add default ramp_delay, add comment for go bit] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped the enable/disable code. - Added default ramp_delay value. - Added comment for the "go bit".

[PATCH v2 02/10] regulator: add support for SY8106A regulator

code, add default ramp_delay, add comment for go bit] Signed-off-by: Icenowy Zheng --- Changes in v2: - Dropped the enable/disable code. - Added default ramp_delay value. - Added comment for the "go bit". drivers/regulator/Kconfig | 8 +- drivers/regulator/Makefile

[PATCH v2 01/10] dt-bindings: add binding for the SY8106A voltage regulator

From: Ondrej Jirman <meg...@megous.com> SY8106A is an I2C-controlled adjustable voltage regulator made by Silergy Corp. Add its device tree binding. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change commit message and slight fixes] Signed-off-by: Icenowy Zheng <

[PATCH v2 01/10] dt-bindings: add binding for the SY8106A voltage regulator

From: Ondrej Jirman SY8106A is an I2C-controlled adjustable voltage regulator made by Silergy Corp. Add its device tree binding. Signed-off-by: Ondrej Jirman [Icenowy: Change commit message and slight fixes] Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai Acked-by: Rob Herring

[PATCH v2 00/10] Allwinner H3 DVFS support

. Then there's patches for several tested boards: Orange Pi PC (with SY8106A), Orange Pi One/Zero (with GPIO-adjustable SY8113B) and ALL-H3-CC (unadjustable). Icenowy Zheng (5): ARM: sun8i: h3: add operating-points-v2 table for CPU ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board ARM

[PATCH v2 00/10] Allwinner H3 DVFS support

. Then there's patches for several tested boards: Orange Pi PC (with SY8106A), Orange Pi One/Zero (with GPIO-adjustable SY8113B) and ALL-H3-CC (unadjustable). Icenowy Zheng (5): ARM: sun8i: h3: add operating-points-v2 table for CPU ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board ARM

Re: [PATCH 2/3] ARM: dts: sun8i: add audio codec support into V3s DTSI

于 2018年2月3日 GMT+08:00 上午3:49:35, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Fri, Feb 02, 2018 at 10:01:52PM +0800, Icenowy Zheng wrote: >> Allwinner V3s SoC features an internal audio codec like the one in >H3, >> and a analog codec like the one in H3/A23 (but m

Re: [PATCH 2/3] ARM: dts: sun8i: add audio codec support into V3s DTSI

于 2018年2月3日 GMT+08:00 上午3:49:35, Maxime Ripard 写到: >On Fri, Feb 02, 2018 at 10:01:52PM +0800, Icenowy Zheng wrote: >> Allwinner V3s SoC features an internal audio codec like the one in >H3, >> and a analog codec like the one in H3/A23 (but much simpler). >> >

Re: [PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

于 2018年2月5日 GMT+08:00 下午4:55:58, Emmanuel Vadot <m...@bidouilliste.com> 写到: > > Hello, > >On Sat, 3 Feb 2018 19:23:53 +0800 >Icenowy Zheng <icen...@aosc.io> wrote: > >> This reverts commit 7daa213700758b5b08fc0daab09bb139dd334165. >> >> The or

Re: [PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

于 2018年2月5日 GMT+08:00 下午4:55:58, Emmanuel Vadot 写到: > > Hello, > >On Sat, 3 Feb 2018 19:23:53 +0800 >Icenowy Zheng wrote: > >> This reverts commit 7daa213700758b5b08fc0daab09bb139dd334165. >> >> The original commit has several problems: >>

[PATCH v2 5/6] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2 5/6] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng --- Changes

[PATCH v2 6/6] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by:

[PATCH v2 6/6] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by: Ic

[PATCH v2 1/6] pinctrl: sunxi: support pin controllers with holes among IRQ banks

to hardware IRQ bank map, so the new situation in H6 main pin controller can be processed. The old special situation which uses a constant offset (on A33 and V3s, both with a offset of 1) can be also processed with the new code. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- No changes

[PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Exported APB1 bus clock for PIO. - Switch to SPDX license identifier. .../devicetree/bindings/clock

[PATCH v2 1/6] pinctrl: sunxi: support pin controllers with holes among IRQ banks

to hardware IRQ bank map, so the new situation in H6 main pin controller can be processed. The old special situation which uses a constant offset (on A33 and V3s, both with a offset of 1) can be also processed with the new code. Signed-off-by: Icenowy Zheng --- No changes in v2. drivers/pinctrl/sunxi

[PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng --- Changes in v2: - Exported APB1 bus clock for PIO. - Switch to SPDX license identifier. .../devicetree/bindings/clock/sunxi-ccu.txt|1

[PATCH v2 0/6] Initial Allwinner H6 support

). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (6): pinctrl: sunxi: support pin controllers with holes among IRQ banks pinctrl: sunxi: add support for the Allwinner H6 main pin controller clk

[PATCH v2 3/6] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- No changes in v2. drivers/clk/sunxi-ng/ccu_nkmp.

[PATCH v2 3/6] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- No changes in v2. drivers/clk/sunxi-ng/ccu_nkmp.c | 20

[PATCH v2 0/6] Initial Allwinner H6 support

). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (6): pinctrl: sunxi: support pin controllers with holes among IRQ banks pinctrl: sunxi: add support for the Allwinner H6 main pin controller clk

[PATCH v2 2/6] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

t. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped without_bus_gate description. - Switched to SPDX license identifier. .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctr

[PATCH v2 2/6] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

t. Signed-off-by: Icenowy Zheng --- Changes in v2: - Dropped without_bus_gate description. - Switched to SPDX license identifier. .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile

[PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

) are not considered, and will fail to work after adding this commit. This indicates that this patch should be not tested at all. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 57 1 file changed, 57 deletions(-)

[PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

) are not considered, and will fail to work after adding this commit. This indicates that this patch should be not tested at all. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 57 1 file changed, 57 deletions(-) diff --git a/arch/arm

Re: [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 上午6:13:01, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Sat, Feb 03, 2018 at 02:04:54AM +0800, Icenowy Zheng wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the same capability with H3. The V

Re: [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 上午6:13:01, Maxime Ripard 写到: >On Sat, Feb 03, 2018 at 02:04:54AM +0800, Icenowy Zheng wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the same capability with H3. The V3s just doesn't wire out >> the

Re: [linux-sunxi] [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 下午2:00:33, Julian Calaby <julian.cal...@gmail.com> 写到: >Hi Icenowy, > >On Sat, Feb 3, 2018 at 5:04 AM, Icenowy Zheng <icen...@aosc.io> wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the s

Re: [linux-sunxi] [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 下午2:00:33, Julian Calaby 写到: >Hi Icenowy, > >On Sat, Feb 3, 2018 at 5:04 AM, Icenowy Zheng wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the same capability with H3. The V3s just doesn't wire out

[PATCH 2/3] ARM: sun8i: v3s: add V3s EMAC device tree node

The V3/V3s EMAC is just similar to the one in H3 SoC, but as the package of V3s is pin-limited, the external MII/MDIO bus is not wired out. Add V3s EMAC device tree node. As V3s is only capable of using the internal PHY, it's hardcoded in the V3s DTSI file. Signed-off-by: Icenowy Zheng <i

[PATCH 2/3] ARM: sun8i: v3s: add V3s EMAC device tree node

The V3/V3s EMAC is just similar to the one in H3 SoC, but as the package of V3s is pin-limited, the external MII/MDIO bus is not wired out. Add V3s EMAC device tree node. As V3s is only capable of using the internal PHY, it's hardcoded in the V3s DTSI file. Signed-off-by: Icenowy Zheng

[PATCH 3/3] ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock

The Lichee Pi Zero Dock has an Ethernet port connected to the internal PHY of the V3s SoC. Enable it in the device tree. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 8 1 file changed, 8 insertions(+) diff --git a/ar

[PATCH 3/3] ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock

The Lichee Pi Zero Dock has an Ethernet port connected to the internal PHY of the V3s SoC. Enable it in the device tree. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s

[PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

all capabilities. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 ++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/Documen

[PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

all capabilities. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 ++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net

[PATCH 0/3] Allwinner V3s EMAC support

support for V3. Icenowy Zheng (3): net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one ARM: sun8i: v3s: add V3s EMAC device tree node ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock .../devicetree/bindings/net/dwmac-sun8i.txt| 10 ++-- arch/arm/boot/dts/sun8i

[PATCH 0/3] Allwinner V3s EMAC support

support for V3. Icenowy Zheng (3): net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one ARM: sun8i: v3s: add V3s EMAC device tree node ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock .../devicetree/bindings/net/dwmac-sun8i.txt| 10 ++-- arch/arm/boot/dts/sun8i

[PATCH 3/3] ARM: sun8i: v3s: enable audio on Lichee Pi Zero Dock board

The Lichee Pi Zero Dock board has an audio jack and an onboard MIC. Enable them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-do

[PATCH 3/3] ARM: sun8i: v3s: enable audio on Lichee Pi Zero Dock board

The Lichee Pi Zero Dock board has an audio jack and an onboard MIC. Enable them. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot

[PATCH 2/3] ARM: dts: sun8i: add audio codec support into V3s DTSI

Allwinner V3s SoC features an internal audio codec like the one in H3, and a analog codec like the one in H3/A23 (but much simpler). Add them in the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++ 1 file chang

[PATCH 2/3] ARM: dts: sun8i: add audio codec support into V3s DTSI

Allwinner V3s SoC features an internal audio codec like the one in H3, and a analog codec like the one in H3/A23 (but much simpler). Add them in the DTSI file. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++ 1 file changed, 19 insertions(+) diff

[PATCH 1/3] ARM: dts: sun8i: add DMA engine in V3s DTSI

Allwinner V3s SoC features a DMA engine. Add it in the DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi

[PATCH 1/3] ARM: dts: sun8i: add DMA engine in V3s DTSI

Allwinner V3s SoC features a DMA engine. Add it in the DTSI file. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 443b083c6adc..20edebd983f0

[PATCH 0/3] Allwinner V3s audio codec device tree changes

jack and on-board mic. Icenowy Zheng (3): ARM: dts: sun8i: add DMA engine in V3s DTSI ARM: dts: sun8i: add audio codec support into V3s DTSI ARM: sun8i: v3s: enable audio on Lichee Pi Zero Dock board arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 +++ arch/arm/boot/dts/sun8i

[PATCH 0/3] Allwinner V3s audio codec device tree changes

jack and on-board mic. Icenowy Zheng (3): ARM: dts: sun8i: add DMA engine in V3s DTSI ARM: dts: sun8i: add audio codec support into V3s DTSI ARM: sun8i: v3s: enable audio on Lichee Pi Zero Dock board arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 +++ arch/arm/boot/dts/sun8i

Re: [linux-sunxi] Re: [PATCH v3 06/12] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline

于 2018年1月30日 GMT+08:00 上午2:05:26, Rob Herring 写到: >On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote: >> This commit adds all necessary compatibles and descriptions needed to >> implement A83T HDMI pipeline. >> >> Mixer is already properly described, so only

Re: [linux-sunxi] Re: [PATCH v3 06/12] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline

于 2018年1月30日 GMT+08:00 上午2:05:26, Rob Herring 写到: >On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote: >> This commit adds all necessary compatibles and descriptions needed to >> implement A83T HDMI pipeline. >> >> Mixer is already properly described, so only compatible is added.

Re: [PATCH 07/16] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data

于 2018年1月28日 GMT+08:00 下午9:46:18, Philipp Rossak 写到: > > >On 28.01.2018 10:02, Jonathan Cameron wrote: >> On Fri, 26 Jan 2018 16:19:32 +0100 >> Philipp Rossak wrote: >> >>> This patch reworks the driver to support nvmem calibration cells. >>> The driver

Re: [PATCH 07/16] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data

于 2018年1月28日 GMT+08:00 下午9:46:18, Philipp Rossak 写到: > > >On 28.01.2018 10:02, Jonathan Cameron wrote: >> On Fri, 26 Jan 2018 16:19:32 +0100 >> Philipp Rossak wrote: >> >>> This patch reworks the driver to support nvmem calibration cells. >>> The driver checks if the nvmem calibration is

Re: [PATCH 04/16] iio: adc: sun4i-gpadc-iio: rework: sampling start/end code readout reg

ensor some basic rework of the code is necessary. >>> >>> This commit reworks the code and allows the sampling start/end code >and >>> the position of value readout register to be altered. Later the >start/end >>> functions will be used to configure the ths and start/st

Re: [PATCH 04/16] iio: adc: sun4i-gpadc-iio: rework: sampling start/end code readout reg

; >>> This commit reworks the code and allows the sampling start/end code >and >>> the position of value readout register to be altered. Later the >start/end >>> functions will be used to configure the ths and start/stop the >>> sampling. >>> >>

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

在 2018年1月25日星期四 CST 下午11:35:20，Maxime Ripard 写道： > Hi, > > On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote: > > 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： > > > > > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: > >

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

在 2018年1月25日星期四 CST 下午11:35:20，Maxime Ripard 写道： > Hi, > > On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote: > > 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： > > > > > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: > >

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

于 2018年1月25日 GMT+08:00 下午11:35:20, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote: >> 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： >> > On Sat, Jan 20, 2018 at 07:17:2

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

于 2018年1月25日 GMT+08:00 下午11:35:20, Maxime Ripard 写到: >Hi, > >On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote: >> 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： >> > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: >> > &

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: > > This is the RFC initial patchset for the "new" Allwinner SUNIV ARM9 SoC. > > > > The same die is packaged differently, come with different

Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道： > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: > > This is the RFC initial patchset for the "new" Allwinner SUNIV ARM9 SoC. > > > > The same die is packaged differently, come with different

[PATCH] nvmem: sunxi-sid: fix H3 SID controller support

It seems that doing some operation will make the value pre-read on H3 SID controller wrong again, so all operation should be performed by register. Change the SID reading to use register only. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/nvmem/sunxi_sid.

[PATCH] nvmem: sunxi-sid: fix H3 SID controller support

It seems that doing some operation will make the value pre-read on H3 SID controller wrong again, so all operation should be performed by register. Change the SID reading to use register only. Signed-off-by: Icenowy Zheng --- drivers/nvmem/sunxi_sid.c | 71

Re: [linux-sunxi] [RFC PATCH 2/9] ARM: sunxi: add Allwinner ARMv5 SoCs

于 2018年1月20日 GMT+08:00 上午11:06:40, Julian Calaby <julian.cal...@gmail.com> 写到: >Hi Icenowy, > >On Sat, Jan 20, 2018 at 10:17 AM, Icenowy Zheng <icen...@aosc.io> >wrote: >> Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die >used >> fo

Re: [linux-sunxi] [RFC PATCH 2/9] ARM: sunxi: add Allwinner ARMv5 SoCs

于 2018年1月20日 GMT+08:00 上午11:06:40, Julian Calaby 写到: >Hi Icenowy, > >On Sat, Jan 20, 2018 at 10:17 AM, Icenowy Zheng >wrote: >> Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die >used >> for many new F-series products, including F1C100A, F1C100s,

[RFC PATCH 4/9] clocksource: sun4i: add a compatible for suniv

The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- d

[RFC PATCH 4/9] clocksource: sun4i: add a compatible for suniv

The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. Signed-off-by: Icenowy Zheng --- drivers/clocksource

[RFC PATCH 6/9] pinctrl: sunxi: add support for suniv (newer F-series SoCs)

The suniv chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile| 1 + drivers/pinctrl

[RFC PATCH 6/9] pinctrl: sunxi: add support for suniv (newer F-series SoCs)

The suniv chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile| 1 + drivers/pinctrl/sunxi/pinctrl-suniv.c

[RFC PATCH 7/9] clk: sunxi-ng: add support for suniv SoC

The suniv SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/su

[RFC PATCH 8/9] ARM: dts: suniv: add initial DTSI file for suniv and F1C100s

As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As there's nothing special for it, add a dummy DTSI file for it. Signed-off-by: Icenowy Zheng <icen...@aosc

[RFC PATCH 7/9] clk: sunxi-ng: add support for suniv SoC

The suniv SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile

[RFC PATCH 8/9] ARM: dts: suniv: add initial DTSI file for suniv and F1C100s

As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As there's nothing special for it, add a dummy DTSI file for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts

[RFC PATCH 9/9] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano

Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f

[RFC PATCH 9/9] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano

Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi

[RFC PATCH 5/9] clocksource/drivers/sun4i: register as sched_clock on suniv

The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clocksource/sun4i_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 de

[RFC PATCH 5/9] clocksource/drivers/sun4i: register as sched_clock on suniv

The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Icenowy Zheng --- drivers/clocksource/sun4i_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[RFC PATCH 2/9] ARM: sunxi: add Allwinner ARMv5 SoCs

Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/mach-sunxi/Kconfig| 13 + arch/arm/mach-sunxi/Makefile

[RFC PATCH 2/9] ARM: sunxi: add Allwinner ARMv5 SoCs

Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/Kconfig| 13 + arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach

[RFC PATCH 3/9] irqchip/sun4i: add support for suniv interrupt controller

The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13. Add support for it in irq-sun4i driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/irqchip/irq-sun4i.c | 43 ++- 1 file c

[RFC PATCH 3/9] irqchip/sun4i: add support for suniv interrupt controller

The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13. Add support for it in irq-sun4i driver. Signed-off-by: Icenowy Zheng --- drivers/irqchip/irq-sun4i.c | 43 ++- 1 file changed, 38 insertions

[RFC PATCH 1/9] ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs

CONFIG_ARCH_SUNXI_V7 option. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/configs/multi_v7_defconfig | 2 +- arch/arm/configs/sunxi_defconfig| 2 +- arch/arm/mach-sunxi/Kconfig | 14 -- arch/arm/mach-sunxi/Makefile| 2 +- 4 files chang

[RFC PATCH 1/9] ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs

CONFIG_ARCH_SUNXI_V7 option. Signed-off-by: Icenowy Zheng --- arch/arm/configs/multi_v7_defconfig | 2 +- arch/arm/configs/sunxi_defconfig| 2 +- arch/arm/mach-sunxi/Kconfig | 14 -- arch/arm/mach-sunxi/Makefile| 2 +- 4 files changed, 15 insertions(+), 5

[RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

imer, like the sun4i/5i Cortex-A8 SoCs. So adapt the IRQ and timer driver used by sun4i/5i to support suniv. This is PATCH 3~5. Then it's the common way to support a new SoC -- pinctrl, CCU and initial DT. Icenowy Zheng (9): ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner

[RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC

imer, like the sun4i/5i Cortex-A8 SoCs. So adapt the IRQ and timer driver used by sun4i/5i to support suniv. This is PATCH 3~5. Then it's the common way to support a new SoC -- pinctrl, CCU and initial DT. Icenowy Zheng (9): ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner

Re: [PATCH v5 1/2] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)

在 2018年1月20日星期六 CST 上午5:14:09，Rob Herring 写道： > On Thu, Jan 11, 2018 at 11:03:43AM +0800, Yong Deng wrote: > > Add binding documentation for Allwinner V3s CSI. > > > > Signed-off-by: Yong Deng > > --- > > > > .../devicetree/bindings/media/sun6i-csi.txt| 59 > >

Re: [PATCH v5 1/2] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)

在 2018年1月20日星期六 CST 上午5:14:09，Rob Herring 写道： > On Thu, Jan 11, 2018 at 11:03:43AM +0800, Yong Deng wrote: > > Add binding documentation for Allwinner V3s CSI. > > > > Signed-off-by: Yong Deng > > --- > > > > .../devicetree/bindings/media/sun6i-csi.txt| 59 > > ++ 1

Re: [RESEND] phy: sun4i-usb: add support for R40 USB PHY

于 2018年1月19日 GMT+08:00 下午2:25:09, Chen-Yu Tsai <w...@csie.org> 写到: >Hi Kishon, > >On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer ><hermann.la...@iwr.uni-heidelberg.de> wrote: >> On Wed, Jan 03, 2018 at 04:49:44PM +0800, Icenowy Zheng wrote: >>> Allwin

Re: [RESEND] phy: sun4i-usb: add support for R40 USB PHY

于 2018年1月19日 GMT+08:00 下午2:25:09, Chen-Yu Tsai 写到: >Hi Kishon, > >On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer > wrote: >> On Wed, Jan 03, 2018 at 04:49:44PM +0800, Icenowy Zheng wrote: >>> Allwinner R40 features a USB PHY like the one in A64, but with 3

Re: [PATCH v2] arm64: allwinner: a64: orangepi-zero-plus2: add usb otg

在 2018年1月15日星期一 CST 下午4:01:39，Maxime Ripard 写道： > Hi, > > On Fri, Jan 12, 2018 at 02:39:04PM +0530, Jagan Teki wrote: > > Add usb otg support for orangepi-zero-plus2 board: > > - Add usb_otg node with dr_mode as 'otg' > > - USB0-IDDET connected to PA21 > > - VBUS connected through DCIN which

Re: [PATCH v2] arm64: allwinner: a64: orangepi-zero-plus2: add usb otg

在 2018年1月15日星期一 CST 下午4:01:39，Maxime Ripard 写道： > Hi, > > On Fri, Jan 12, 2018 at 02:39:04PM +0530, Jagan Teki wrote: > > Add usb otg support for orangepi-zero-plus2 board: > > - Add usb_otg node with dr_mode as 'otg' > > - USB0-IDDET connected to PA21 > > - VBUS connected through DCIN which

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

于 2018年1月11日 GMT+08:00 下午7:48:40, Andre Przywara <andre.przyw...@arm.com> 写到: >Hi, > >another take to avoid this patch at all, I just remembered this from an >IRC discussion before: > >On 06/01/18 04:23, Icenowy Zheng wrote: >> The Allwinner H6 pin controllers (both

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

于 2018年1月11日 GMT+08:00 下午7:48:40, Andre Przywara 写到: >Hi, > >another take to avoid this patch at all, I just remembered this from an >IRC discussion before: > >On 06/01/18 04:23, Icenowy Zheng wrote: >> The Allwinner H6 pin controllers (both the main one and the CPUs

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

> >> Hi, > > >> > > >> On 06/01/18 04:23, Icenowy Zheng wrote: > > >>> The Allwinner H6 pin controllers (both the main one and the CPUs one) > > >>> have no bus gate clocks. > > >>> > > >>> Add support for

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

在 2018年1月11日星期四 CST 下午6:41:00，Maxime Ripard 写道： > On Thu, Jan 11, 2018 at 10:23:52AM +, Andre Przywara wrote: > > Hi, > > > > On 11/01/18 10:14, Chen-Yu Tsai wrote: > > > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara wrote: > > >> Hi, > > &

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara <andre.przyw...@arm.com> 写到: >Hi, > >On 06/01/18 04:23, Icenowy Zheng wrote: >> The Allwinner H6 pin controllers (both the main one and the CPUs one) >> have no bus gate clocks. >> >> Add support for this

Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate

于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到: >Hi, > >On 06/01/18 04:23, Icenowy Zheng wrote: >> The Allwinner H6 pin controllers (both the main one and the CPUs one) >> have no bus gate clocks. >> >> Add support for this kind of pin controllers. &g

Re: [linux-sunxi] Re: [PATCH 0/7] Initial Allwinner H6 support

在 2018年1月11日星期四 CST 下午5:36:39，Linus Walleij 写道： > On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng <icen...@aosc.io> wrote: > > This patchset adds initial support for the Allwinner H6 SoC. > > Can I apply the pin control patches without the clock patches? I think it's OK. No

Re: [linux-sunxi] Re: [PATCH 0/7] Initial Allwinner H6 support

在 2018年1月11日星期四 CST 下午5:36:39，Linus Walleij 写道： > On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng wrote: > > This patchset adds initial support for the Allwinner H6 SoC. > > Can I apply the pin control patches without the clock patches? I think it's OK. Note: on H6 now the pi

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