The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 454de1e7d970d6bc567686052329e4814842867c
Gitweb:
https://git.kernel.org/tip/454de1e7d970d6bc567686052329e4814842867c
Author:Janakarajan Natarajan
AuthorDate:Mon, 07 Oct 2019 19:00:22
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 454de1e7d970d6bc567686052329e4814842867c
Gitweb:
https://git.kernel.org/tip/454de1e7d970d6bc567686052329e4814842867c
Author:Janakarajan Natarajan
AuthorDate:Mon, 07 Oct 2019 19:00:22
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 9b69cab42e5d14b8f0467566e3d97e682365db2d
Gitweb:
https://git.kernel.org/tip/9b69cab42e5d14b8f0467566e3d97e682365db2d
Author:Janakarajan Natarajan
AuthorDate:Mon, 07 Oct 2019 19:00:22
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 9b69cab42e5d14b8f0467566e3d97e682365db2d
Gitweb:
https://git.kernel.org/tip/9b69cab42e5d14b8f0467566e3d97e682365db2d
Author:Janakarajan Natarajan
AuthorDate:Mon, 07 Oct 2019 19:00:22
On 7/11/2019 10:10 PM, Viresh Kumar wrote:
> On 11-07-19, 16:58, Janakarajan Natarajan wrote:
>> On 7/11/2019 1:12 AM, Viresh Kumar wrote:
>>> On 10-07-19, 18:37, Natarajan, Janakarajan wrote:
>>>> +static int amd_cpufreq_cpu_init(struct cpufreq_policy *po
icitly enabled
>> + */
>> +if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
>> +boot_cpu_data.x86 < 0x17 || !cppc_enable)
>> +return -ENODEV;
>> +
>> +ret = cpufreq_register_driver(_cpufreq_driver);
>> +if (ret) {
>> +pr_info("Failed to register driver\n");
>> +goto out;
>> +}
>> +
>> +ret = amd_cpufreq_sysfs_expose_params();
>> +if (ret) {
>> +pr_info("Could not create sysfs entries\n");
>> +cpufreq_unregister_driver(_cpufreq_driver);
>> +goto out;
>> +}
>> +
>> +pr_info("Using amd-cpufreq driver\n");
>> +return ret;
>> +
>> +out:
>> +return ret;
>> +}
>> +
>> +static void __exit amd_cpufreq_exit(void)
>> +{
>> +amd_cpufreq_sysfs_delete_params();
>> +cpufreq_unregister_driver(_cpufreq_driver);
>> +}
>> +
>> +static const struct acpi_device_id amd_acpi_ids[] __used = {
>> +{ACPI_PROCESSOR_DEVICE_HID, },
>> +{}
>> +};
>> +
>> +device_initcall(amd_cpufreq_init);
>> +module_exit(amd_cpufreq_exit);
>> +MODULE_DEVICE_TABLE(acpi, amd_acpi_ids);
> All three should be placed directly below the struct/function they
> represent without any blank lines in between. As suggested in
> kernel documentation.
>
>> +
>> +MODULE_AUTHOR("Janakarajan Natarajan");
>> +MODULE_DESCRIPTION("AMD CPUFreq driver based on ACPI CPPC v6.1 spec");
>> +MODULE_LICENSE("GPL");
> Should this be "GPL v2" ?
>
>> --
>> 2.17.1
kernel.
>
> v1->v2:
> * Add macro to ensure BUFFER only registers have BUFFER type.
> * Add support macro to make the right check based on register type.
> * Remove support checks for registers which are mandatory.
Are there any concerns regarding this patchset?
Thanks.
Commit-ID: 08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Gitweb: https://git.kernel.org/tip/08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Author: Janakarajan Natarajan
AuthorDate: Wed, 7 Nov 2018 20:59:07 +
Committer: Borislav Petkov
CommitDate: Wed, 7 Nov 2018 22:21:03 +0100
x86
Commit-ID: 08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Gitweb: https://git.kernel.org/tip/08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Author: Janakarajan Natarajan
AuthorDate: Wed, 7 Nov 2018 20:59:07 +
Committer: Borislav Petkov
CommitDate: Wed, 7 Nov 2018 22:21:03 +0100
x86
In Family 17h, some L3 Cache Performance events require the ThreadMask
and SliceMask to be set. For other events, these fields do not affect
the count either way.
Set ThreadMask and SliceMask to 0xFF and 0xF respectively.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/events/amd/uncore.c
In Family 17h, some L3 Cache Performance events require the ThreadMask
and SliceMask to be set. For other events, these fields do not affect
the count either way.
Set ThreadMask and SliceMask to 0xFF and 0xF respectively.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/events/amd/uncore.c
"depends on" to "select" for SEV")
Cc: # 4.16.x
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 92fd433..1bbec38 100644
--- a/arch/x86/kvm/K
"depends on" to "select" for SEV")
Cc: # 4.16.x
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 92fd433..1bbec38 100644
--- a/arch/x86/kvm/K
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/cc
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp-sev.h | 11 +++
include/uapi
the
Chip Endorsment Key (CEK) public key signed by the AMD SEV Signing Key
(ASK).
v1->v2:
* Added cover letter.
* Misc changes based on Boris' feedback.
Janakarajan Natarajan (2):
crypto: ccp: Add DOWNLOAD_FIRMWARE SEV command
crypto: ccp: Add GET_ID SEV command
drivers/crypto/ccp/psp-de
the
Chip Endorsment Key (CEK) public key signed by the AMD SEV Signing Key
(ASK).
v1->v2:
* Added cover letter.
* Misc changes based on Boris' feedback.
Janakarajan Natarajan (2):
crypto: ccp: Add DOWNLOAD_FIRMWARE SEV command
crypto: ccp: Add GET_ID SEV command
drivers/crypto/ccp/psp-de
quot;select" for SEV")
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 92fd433..d9b16b7 100644
--- a/arch/x86/kvm/Kconfig
quot;select" for SEV")
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 92fd433..d9b16b7 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -85
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp-sev.h | 11 +++
include/uapi
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/cc
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp
refer to "Section 5.12 GET_ID" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-dev.c | 44
include/linux/psp-sev.h | 11 +++
include/uapi
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
drivers/crypto/cc
compared to the existing firmware.
For more information please refer to "Section 5.11 DOWNLOAD_FIRMWARE" of
https://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf
Signed-off-by: Janakarajan Natarajan
---
drivers/crypto/ccp/psp-
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan <janakarajan.nat
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..de561d4
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..de561d4 100644
--- a/arch/x86/kvm/cpuid.c
+++ b
* Rebased to latest KVM tree.
v4->v5:
* Removed conditional check when exposing Perf Extension flag to
guests based on Radim's feedback.
Janakarajan Natarajan (3):
x86/msr: Add AMD Core Perf Extension MSRs
x86/kvm: Add support for AMD Core Perf Extension in guest
x86/kvm: Expose AMD Core Pe
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/inclu
* Rebased to latest KVM tree.
v4->v5:
* Removed conditional check when exposing Perf Extension flag to
guests based on Radim's feedback.
Janakarajan Natarajan (3):
x86/msr: Add AMD Core Perf Extension MSRs
x86/kvm: Add support for AMD Core Perf Extension in guest
x86/kvm: Expose AMD Core Pe
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e7b983a
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan <janakarajan.nat
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm
* Rebased to latest KVM tree.
Janakarajan Natarajan (3):
x86/msr: Add AMD Core Perf Extension MSRs
x86/kvm: Add support for AMD Core Perf Extension in guest
x86/kvm: Expose AMD Core Perf Extension flag to guests
arch/x86/include/asm/msr-index.h | 14
arch/x86/kvm/cpuid.c | 8
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8
* Rebased to latest KVM tree.
Janakarajan Natarajan (3):
x86/msr: Add AMD Core Perf Extension MSRs
x86/kvm: Add support for AMD Core Perf Extension in guest
x86/kvm: Expose AMD Core Perf Extension flag to guests
arch/x86/include/asm/msr-index.h | 14
arch/x86/kvm/cpuid.c | 8
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8c95a7c 100644
--- a/arch/x86/kvm/cpuid.c
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/inclu
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e7b983a
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan <janakarajan.nat
[] is changed.
New functions are added to check the validity of the get/set MSRs.
If the guest has the X86_FEATURE_PERFCTR_CORE cpuid flag set, the number
of counters available to the vcpu is set to 6. It the flag is not set
then it is 4.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm
.
v1->v2:
* Rearranged MSR #defines based on Boris's suggestion.
v2->v3:
* Changed the logic of mapping MSR to gp_counters[] index based on
Boris's feedback.
* Removed use of family checks based on Radim's feedback.
* Removed KVM bugfix patch since it is already applied.
Janakarajan Natara
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/inclu
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8
.
v1->v2:
* Rearranged MSR #defines based on Boris's suggestion.
v2->v3:
* Changed the logic of mapping MSR to gp_counters[] index based on
Boris's feedback.
* Removed use of family checks based on Radim's feedback.
* Removed KVM bugfix patch since it is already applied.
Janakarajan Natara
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 34c4922
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8c95a7c 100644
--- a/arch/x86/kvm/cpuid.c
I forgot to add Boris's Reviewed-by Tag. If the patchset is acceptable,
please let me know if I should send another version with the Tag or if
the Tag can be added when it is merged.
On 11/06/2017 11:44 AM, Janakarajan Natarajan wrote:
The function for CPUID 8001 ECX is set to 0xc001
I forgot to add Boris's Reviewed-by Tag. If the patchset is acceptable,
please let me know if I should send another version with the Tag or if
the Tag can be added when it is merged.
On 11/06/2017 11:44 AM, Janakarajan Natarajan wrote:
The function for CPUID 8001 ECX is set to 0xc001
[]
is changed.
Additionally, a fix is provided for CPUID_8000_0001_ECX in reverse_cpuid[]
to change the CPUID function from 0xc001 to 0x8001.
This patchset has been tested with Family 17h and Opteron G1 guests.
v1->v2:
* Rearranged MSR #defines based on Boris's suggestion.
Janakarajan Natara
[]
is changed.
Additionally, a fix is provided for CPUID_8000_0001_ECX in reverse_cpuid[]
to change the CPUID function from 0xc001 to 0x8001.
This patchset has been tested with Family 17h and Opteron G1 guests.
v1->v2:
* Rearranged MSR #defines based on Boris's suggestion.
Janakarajan Natara
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/inclu
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 17f5c12
off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/pmu_amd.c | 133 +++--
arch/x86/kvm/x86.c | 1 +
2 files changed, 120 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kvm/pmu_amd.c b/arch/x86/kvm/pmu_amd.c
inde
off-by: Janakarajan Natarajan
---
arch/x86/kvm/pmu_amd.c | 133 +++--
arch/x86/kvm/x86.c | 1 +
2 files changed, 120 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kvm/pmu_amd.c b/arch/x86/kvm/pmu_amd.c
index cd94443..2c694446 100644
--- a/a
The function for CPUID 8001 ECX is set to 0xc001. Set it to
0x8001.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
The function for CPUID 8001 ECX is set to 0xc001. Set it to
0x8001.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 0bc5c13..b21b1d2 100644
--- a/arch
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8c95a7c 100644
--- a/arch/x86/kvm/cpuid.c
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/msr-index.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/inclu
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 17f5c12
[]
is changed.
Additionally, a fix is provided for CPUID_8000_0001_ECX in reverse_cpuid[]
to change the CPUID function from 0xc001 to 0x8001.
This patchset has been tested with Family 17h and Opteron G1 guests.
Janakarajan Natarajan (4):
x86/kvm/cpuid: Fix CPUID function for word 6
[]
is changed.
Additionally, a fix is provided for CPUID_8000_0001_ECX in reverse_cpuid[]
to change the CPUID function from 0xc001 to 0x8001.
This patchset has been tested with Family 17h and Opteron G1 guests.
Janakarajan Natarajan (4):
x86/kvm/cpuid: Fix CPUID function for word 6
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8
off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/pmu_amd.c | 133 +++--
arch/x86/kvm/x86.c | 1 +
2 files changed, 120 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kvm/pmu_amd.c b/arch/x86/kvm/pmu_amd.c
inde
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0099e10..8c95a7c 100644
--- a/arch/x86/kvm/cpuid.c
off-by: Janakarajan Natarajan
---
arch/x86/kvm/pmu_amd.c | 133 +++--
arch/x86/kvm/x86.c | 1 +
2 files changed, 120 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kvm/pmu_amd.c b/arch/x86/kvm/pmu_amd.c
index cd94443..2c694446 100644
--- a/a
The function for CPUID 8001 ECX is set to 0xc001. Set it to
0x8001.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/kvm/cpuid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
The function for CPUID 8001 ECX is set to 0xc001. Set it to
0x8001.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/kvm/cpuid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 0bc5c13..b21b1d2 100644
--- a/arch
Add a new cpufeature definition for Virtual GIF.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index c
Add a new cpufeature definition for Virtual GIF.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index ca3c48c..0e25e7a 100644
--- a/arch/x86
, the STGI intercept is set. This will assist in opening
the window only when GIF=1.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/svm.h | 6 +
arch/x86/kvm/svm.c | 62 --
2 files chang
, the STGI intercept is set. This will assist in opening
the window only when GIF=1.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/svm.h | 6 +
arch/x86/kvm/svm.c | 62 --
2 files changed, 61 insertions(+), 7 deletions(-)
diff
er-V and KVM as the nested hypervisor.
v1->v2:
* Updated patch description and changed cpufeature definition to be similar
to AMD documentation.
* Updated NMI logic. STGI intercept added to assit in opening NMI window.
Suggested by Radim.
Janakarajan Natarajan (2):
KVM: SVM: Add Virt
er-V and KVM as the nested hypervisor.
v1->v2:
* Updated patch description and changed cpufeature definition to be similar
to AMD documentation.
* Updated NMI logic. STGI intercept added to assit in opening NMI window.
Suggested by Radim.
Janakarajan Natarajan (2):
KVM: SVM: Add Virt
Define a new cpufeature definition for Virtual GIF.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
Define a new cpufeature definition for Virtual GIF.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index ca3c48c..58e7211 100644
--- a/arch
.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/include/asm/svm.h | 6 ++
arch/x86/kvm/svm.c | 47 +++---
2 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/i
.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/svm.h | 6 ++
arch/x86/kvm/svm.c | 47 +++---
2 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 58fffe7
er-V and KVM as the nested hypervisor.
Janakarajan Natarajan (2):
KVM: SVM: Add Virtual GIF feature definition
KVM: SVM: Enable Virtual GIF feature
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/svm.h | 6 +
arch/x86/kvm/svm.c
er-V and KVM as the nested hypervisor.
Janakarajan Natarajan (2):
KVM: SVM: Add Virtual GIF feature definition
KVM: SVM: Enable Virtual GIF feature
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/svm.h | 6 +
arch/x86/kvm/svm.c
Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854
Gitweb: http://git.kernel.org/tip/910448bbed066ab1082b510eef1ae61bb792d854
Author: Janakarajan Natarajan <janakarajan.natara...@amd.com>
AuthorDate: Wed, 14 Jun 2017 11:26:57 -0500
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854
Gitweb: http://git.kernel.org/tip/910448bbed066ab1082b510eef1ae61bb792d854
Author: Janakarajan Natarajan
AuthorDate: Wed, 14 Jun 2017 11:26:57 -0500
Committer: Ingo Molnar
CommitDate: Thu, 10 Aug 2017 12:08:38 +0200
perf/x86/amd
Commit-ID: ab027620e95987b5f0145013090a109b4152d23b
Gitweb: http://git.kernel.org/tip/ab027620e95987b5f0145013090a109b4152d23b
Author: Janakarajan Natarajan <janakarajan.natara...@amd.com>
AuthorDate: Wed, 14 Jun 2017 11:26:58 -0500
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: ab027620e95987b5f0145013090a109b4152d23b
Gitweb: http://git.kernel.org/tip/ab027620e95987b5f0145013090a109b4152d23b
Author: Janakarajan Natarajan
AuthorDate: Wed, 14 Jun 2017 11:26:58 -0500
Committer: Ingo Molnar
CommitDate: Thu, 10 Aug 2017 12:08:39 +0200
perf/x86/amd
over
the cache levels using CPUID 0x801d. The last level cache is the
last value to return a non-zero value in EAX.
Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
---
arch/x86/events/amd/uncore.c | 19 ---
1 file changed, 16 insertions(+), 3 del
over
the cache levels using CPUID 0x801d. The last level cache is the
last value to return a non-zero value in EAX.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/events/amd/uncore.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to
X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
level of cache.
Signed-off-by: Janakarajan Natarajan <janakarajan.nat
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to
X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
level of cache.
Signed-off-by: Janakarajan Natarajan
Reviewed-by: Borislav
.pl and added Reviewed-by tag in patch
description.
v2->v3
* Updated patch description and cleaned up code based on feedback from
Borislav Petkov.
v1->v2
* Replaced while(1) with finite for loop based on feedback from Peter
Zijlstra and Borislav Petkov.
Janakarajan Natarajan (2):
am
.pl and added Reviewed-by tag in patch
description.
v2->v3
* Updated patch description and cleaned up code based on feedback from
Borislav Petkov.
v1->v2
* Replaced while(1) with finite for loop based on feedback from Peter
Zijlstra and Borislav Petkov.
Janakarajan Natarajan (2):
am
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to
X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
level of cache.
Signed-off-by: Janakarajan Natarajan <janakarajan.nat
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to
X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
level of cache.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/events/amd
ion and cleaned up code based on feedback from
Borislav Petkov.
v1->v2
* Replace while(1) with finite for loop based on feedback from Peter
Zijlstra and Borislav Petkov.
Janakarajan Natarajan (2):
amd: uncore: Rename cpufeatures macro for cache counters
amd: uncore: Get correct number of
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