On Tue, 16 Mar 2021 at 08:59, Troy Lee wrote:
>
> Aspeed AST2600 u-boot requires 600KiB+ flash space. Sharing the same
> openbmc-flash-layout-64.dtsi requires to resize the flash partition.
>
> The updated flash layout as follows:
> - u-boot: 896 KiB
> - u-boot-env: 128 KiB
> - kernel: 9MiB
> -
On Thu, 15 Apr 2021 at 14:05, Paul Fertser wrote:
>
> The ADM1278 IC is accessible on I2C bus and on both Wiwynn and Quanta
> Tioga Pass implementations a pair of parallel 0.5 mOhm resistors is used
> for current measurement.
>
> Signed-off-by: Paul Fertser
Thanks, applied.
> ---
>
On Thu, 15 Apr 2021 at 15:53, Konstantin Aladyshev
wrote:
>
> Enable all I2C busses that are used in AMD EthanolX CRB:
> i2c0 - APML P0
> i2c1 - APML P1
> i2c2 - FPGA
> i2c3 - 24LC128 EEPROM
> i2c4 - P0 Power regulators
> i2c5 - P1 Power regulators
> i2c6 - P0/P1 Thermal diode
> i2c7 -
On Fri, 16 Apr 2021 at 00:12, wrote:
>
> From: Tao Ren
>
> Fix the time comparison (timeout vs. max_hw_heartbeat_ms) in set_timeout
> handler to avoid potential integer overflow when the supplied timeout is
> greater than aspeed's maximum allowed timeout (4294 seconds).
>
> Fixes: efa859f7d786
On Mon, 12 Apr 2021 at 02:16, Andrew Jeffery wrote:
> On Thu, 1 Apr 2021, at 15:12, Zev Weiss wrote:
> > + {
> > + status = "okay";
> > + aspeed,sirq-active-high;
>
> This should probably go away, but otherwise,
Zev, this has already been merged (both to mainline for v5.13 and in
On Wed, 7 Apr 2021 at 09:55, William A. Kennington III wrote:
>
> We can't rely on the contents of the devres list during
> spi_unregister_controller(), as the list is already torn down at the
> time we perform devres_find() for devm_spi_release_controller. This
> causes devices registered with
gt; It appears these patches are doing roughly the right thing, and we may still
> > be able to get them into v5.13, but I'm not sure what your plan for
> > maintaining
> > them is. The two options are that you either send your patches to be picked
> > up
> > by Jo
On Thu, 8 Apr 2021 at 23:47, Andrew Jeffery wrote:
> On Thu, 8 Apr 2021, at 21:44, Corey Minyard wrote:
> > On Thu, Apr 08, 2021 at 10:27:46AM +0930, Andrew Jeffery wrote:
> > > > 1. It begins with patches 1-5 put together by Chia-Wei, which I've
> > > > rebased on v5.12-rc2. These fix the
-off-by: Chia-Wei Wang
> Reviewed-by: Andrew Jeffery
Reviewed-by: Joel Stanley
-off-by: Chia-Wei Wang
> Reviewed-by: Andrew Jeffery
> Acked-by: Linus Walleij
Reviewed-by: Joel Stanley
-off-by: Chia-Wei Wang
> Reviewed-by: Andrew Jeffery
> Acked-by: Haiyue Wang
Reviewed-by: Joel Stanley
ted in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
Is this accurate:
The node examples change their reg address to be an offset from the
LPC HC to be an offset from the base of the LPC region.
Reviewed-by: Joel Stanley
>
> Signed-off-by: Chia-Wei Wang
&
On Mon, 5 Apr 2021 at 15:34, Eddie James wrote:
>
> On Tue, 2021-02-09 at 11:12 -0600, Eddie James wrote:
> > In the event that the OCC is not initialized when the driver sends a
> > poll
> > command, the driver may receive an invalid response. This isn't an
> > error
> > condition unless there
On Tue, 9 Feb 2021 at 17:13, Eddie James wrote:
>
> Log an error if the response checksum doesn't match the
> calculated checksum.
Reviewed-by: Joel Stanley
>
> Signed-off-by: Eddie James
> ---
> drivers/fsi/fsi-occ.c | 10 +++---
> 1 file changed, 7 in
On Tue, 9 Feb 2021 at 17:12, Eddie James wrote:
>
> If the OCC is not initialized and responds as such, the driver
> should continue waiting for a valid response until the timeout
> expires.
>
> Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
I guess we should ad
On Thu, 1 Apr 2021 at 00:57, Zev Weiss wrote:
>
> This provides a simple boolean to use instead of the deprecated
> aspeed,sirq-polarity-sense property.
>
> Signed-off-by: Zev Weiss
> ---
> drivers/tty/serial/8250/8250_aspeed_vuart.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
v Weiss
Reviewed-by: Joel Stanley
> ---
> Documentation/devicetree/bindings/serial/8250.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml
> b/Documentation/devicetree/bindings/serial/8250.yaml
> index f54cae9ff7b2..49
h directly without going
through another maintainer. In this case the patch should go through
the aspeed maintainer's tree (me), so you don't need to cc that
address.
> Signed-off-by: Zev Weiss
> Reviewed-by: Joel Stanley
> ---
This spot just here is where you should put the changes between
Hi Anton,
On Thu, 25 Mar 2021 at 01:28, Anton Kachalov wrote:
>
> Gently ping
>
> On Mon, 8 Mar 2021 at 18:11, wrote:
> >
> > From: "Anton D. Kachalov"
> >
> > This change follows OpenBMC partitions' naming layout.
> >
> > Signed-off-by: Anton D. Kachalov
I believe you discussed what
On Wed, 31 Mar 2021 at 07:41, Joel Stanley wrote:
>
> On Tue, 30 Mar 2021 at 00:25, Zev Weiss wrote:
> >
> > This is a relatively low-cost AST2500-based Xeon E-2100/E-2200 series
> > mini-ITX board that we hope can provide a decent platform for OpenBMC
> > dev
On Wed, 31 Mar 2021 at 07:41, Joel Stanley wrote:
>
> On Tue, 30 Mar 2021 at 00:25, Zev Weiss wrote:
> >
> > This is a relatively low-cost AST2500-based Xeon E-2100/E-2200 series
> > mini-ITX board that we hope can provide a decent platform for OpenBMC
> > dev
on for
> basic BMC functionality such as host power control, serial console and
> KVM support, and POST code snooping.
>
> Signed-off-by: Zev Weiss
Reviewed-by: Joel Stanley
> ---
> .../boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 188 ++
> 1 file changed, 188 inser
the lines more obvious.
>
> Signed-off-by: Nichole Wang
Thanks for the patch. The syntax is good, and I will assume the
information is correct. I will apply it to the tree.
Reviewed-by: Joel Stanley
Cheers,
Joel
> ---
> arch/arm/boot/dts/asp
On Mon, 29 Mar 2021 at 12:18, Quan Nguyen wrote:
>
> The SMBus system interface (SSIF) IPMI BMC driver can be used to perform
> in-band IPMI communication with their host in management (BMC) side.
>
> This commits adds support specifically for Aspeed AST2500 which commonly
> used as Board
1d30
> [<7f00deb8>] ast_vhub_ep0_handle_setup+0xa4/0x1bc
> [<7f02ee94>] ast_vhub_dev_irq+0x58/0x84
> [<7f0309e0>] ast_vhub_irq+0xb0/0x1c8
> [<7f02e118>] __handle_irq_event_percpu+0x50/0x19c
> [<8015e5bc>] handle_irq_event_percpu+0x38/0x8c
> [<8015e758
On Tue, 30 Mar 2021 at 22:39, Rob Herring wrote:
>
> On Mon, Mar 29, 2021 at 07:23:37PM -0500, Zev Weiss wrote:
> > Update DT bindings documentation for the new incarnation of the
> > aspeed,sirq-polarity-sense property.
>
> Why?
>
> This isn't a compatible change.
We want to depreciate support
hat should
trigger was not displaying any output).
Adding this patch resolved the issue and the test now passes.
Fixes: 36e2c7421f02 ("fs: don't allow splice read/write without explicit ops")
Signed-off-by: Joel Stanley
---
fs/jffs2/file.c | 1 +
1 file changed, 1 insertion(+)
d
On Wed, 24 Mar 2021 at 22:05, Eddie James wrote:
>
> Updated restricted chips have trouble processing multiple sequenced
> operations. So remove the capability to sequence multiple operations and
> reduce the maximum transfer size to 8 bytes.
>
> Signed-off-by: Eddie James
On Tue, 20 Oct 2020 at 04:14, Joel Stanley wrote:
>
> On Mon, 19 Oct 2020 at 08:57, Dylan Hung wrote:
> >
> > The interrupt handler may set the flag to reset the mac in the future,
> > but that flag is not cleared once the reset has occured.
> >
> > Fixes: 1
On Thu, 4 Mar 2021 at 08:12, Greg Kroah-Hartman
wrote:
>
> On Tue, Mar 02, 2021 at 12:09:21AM +, Yoo, Jae Hyun wrote:
> > > From: Joel Stanley
> > > Jae, John; with this backported do we need to also provide a corresponding
> > > device tree chan
robe?
>
> Fixes: 3772e5da4454 ("drivers/misc: Aspeed LPC snoop output using misc
> chardev")
> Signed-off-by: Jae Hyun Yoo
> Signed-off-by: Vernon Mauery
> Signed-off-by: John Wang
> Reviewed-by: Joel Stanley
> Link:
> https://lore.kernel.org/r/2020120809174
On Tue, 23 Feb 2021 at 08:04, wrote:
>
> From: dingsenjie
>
> remove unneeded variable: "ret".
>
> Signed-off-by: dingsenjie
Thanks for the patch. Instead of removing the unused variable, I think
the code could be improved to return error codes when the recovery
fails.
Cheers,
Joel
> ---
>
Hi Chaiwei,
On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang wrote:
>
> Hi All,
>
> Do you have update on this patch series?
> Aspeed has subsequent LPC module upstream plan.
> We hope that the following patches can be on the basis of the fixed LPC
> layout.
Andrew has expressed his support for your
The last (only?) user of this was removed in commit ba364fc752da ("ARM:
Kirkwood: Remove mach-kirkwood"), back in v3.17.
Signed-off-by: Joel Stanley
---
arch/arm/include/asm/kexec.h| 3 ---
arch/arm/kernel/machine_kexec.c | 8
2 files changed, 11 deletions(-)
diff --git
On Wed, 10 Feb 2021 at 01:43, Arnd Bergmann wrote:
>
> On Sat, Jan 16, 2021 at 2:03 AM Ryan Chen wrote:
> > >
> > > Sorry it did not make it into the merge window. The patch is still in
> > > patchwork.
> > > I could just pick it up directly for v5.12, or wait for a combined pull
> > > request
On Tue, 19 Jan 2021 at 08:14, Geert Uytterhoeven wrote:
>
> Let the LiteX SoC Controller register a restart handler, which resets
> the LiteX SoC by writing 1 to CSR_CTRL_RESET_ADDR.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Joel Stanley
> ---
> v4:
>
On Tue, 19 Jan 2021 at 06:31, Ryan Chen wrote:
>
> Starting from A2, the A-PLL calculation has changed. Use the
> existing formula for A0/A1 and the new formula for A2 onwards.
>
> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
> Signed-off-by: Ryan Chen
On Tue, 19 Jan 2021 at 03:04, Ryan Chen wrote:
>
> > -Original Message-
> > From: Joel Stanley
> > Sent: Tuesday, January 19, 2021 10:20 AM
> > To: Ryan Chen ; Michael Turquette
> > ; Stephen Boyd ;
> > linux-...@vger.kernel.org; linux-kernel@vg
On Mon, 2021-01-18 at 18:08 +0800, Ryan Chen wrote:
> AST2600A1/A2 have different pll calculate formula.
To clarify, only the A0 has the old calculation, and all subsequent
revisions use the new calculation?
If this is the case, do we need to support A0 in mainline linux, or
should we drop
T_VHUB_EP_DMA_CTLSTAT);
This looks correct, as whenever the driver re-enables DMA it uses
ep->epn.dma_conf for the value of this register. So we're not losing
any configuration by setting it to 0.
Acked-by: Joel Stanley
Fixes: 7ecca2a4080c ("usb/gadget: Add driver for Aspeed SoC
On Thu, 7 Jan 2021 at 02:39, ChiaWei Wang wrote:
>
> Hi Rob,
>
> > -Original Message-
> > From: Rob Herring
> > Sent: Wednesday, January 6, 2021 11:32 PM
> > To: ChiaWei Wang
> > Subject: Re: [PATCH 5/6] soc: aspeed: Add eSPI driver
> >
> > On Wed, Jan 06, 2021 at 01:59:38PM +0800,
Currently openrisc will print a message and then hang in an infinite
loop when rebooting.
This patch adopts some code from ARM, which calls the common restart
infrastructure and hangs after a small delay if the restart infra
doesn't do anything.
Signed-off-by: Joel Stanley
---
Geert has a patch
On Tue, 22 Dec 2020 at 19:14, Zev Weiss wrote:
>
> On Mon, Dec 21, 2020 at 10:47:37PM CST, Joel Stanley wrote:
> >On Tue, 15 Dec 2020 at 02:46, Zev Weiss wrote:
> >>
> >> Instead of testing and conditionally clearing them one by one, we can
> >> inst
Build it by default. This is commonly used by fpga targets.
Signed-off-by: Joel Stanley
---
v2: Address review from Masahiro
- Add vmlinux.bin to phony target
- simplfy vmlinux.bin rule
- add cleanup rule
- add vmlinux.bin to targets
- Add gitignore
---
arch/openrisc/Makefile| 12
Build it by default. This is commonly used by fpga targets.
Signed-off-by: Joel Stanley
---
arch/openrisc/Makefile | 7 +++
arch/openrisc/boot/Makefile | 8
2 files changed, 15 insertions(+)
create mode 100644 arch/openrisc/boot/Makefile
diff --git a/arch/openrisc/Makefile b
On Sun, 20 Dec 2020 at 12:40, John Wang wrote:
>
> When aggregating ncsi interfaces and dedicated interfaces to bond
> interfaces, the ncsi response handler will use the wrong net device to
> find ncsi_dev, so that the ncsi interface will not work properly.
> Here, we use the net device
On Tue, 15 Dec 2020 at 02:46, Zev Weiss wrote:
>
> This joins CAPTURE_COMPLETE and FRAME_COMPLETE in the set of interrupts
> that have been seen asserted by the hardware even when disabled, leading
> to the interrupt eventually getting disabled as described in commit
>
unconditionally anyway, so removing the tests provides no change.
Combining them is a good further optimization.
Reviewed-by: Joel Stanley
A question unrelated to this patch: Do you know why the driver doesn't
clear the status bits in the interrupt handler? I would expect it to
write the va
On Tue, 15 Dec 2020 at 02:46, Zev Weiss wrote:
>
> This device seems to have a propensity for asserting interrupts that
> aren't enabled -- in addition to the CAPTURE_COMPLETE and FRAME_COMPLETE
> interrupts squashed in commit 65d270acb2d662c3346793663ac3a759eb4491b8,
> COMP_READY has also been
On Fri, 18 Dec 2020 at 21:40, Zev Weiss wrote:
>
> On Tue, Sep 15, 2020 at 01:45:25PM CDT, Zev Weiss wrote:
> >The ast25xx and ast26xx have, respectively, two and three configurable
> >slave device addresses to the ast24xx's one. We only support using
> >one at a time, but the others may come up
On Mon, 21 Dec 2020 at 17:01, Hongwei Zhang wrote:
>
> Dear Reviewer,
>
> When FTGMAC100 driver is used on other NCSI Ethernet controllers, few
> controllers have compatible issue. One example is Intel I210 Ethernet
> controller on AST2600 BMC, with FTGMAC100 driver, it always trigger
>
On Thu, 17 Dec 2020 at 02:50, Billy Tsai wrote:
>
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
>
> Signed-off-by: Billy Tsai
Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Reviewed-by: Jo
On Fri, 11 Dec 2020 at 03:18, Billy Tsai wrote:
>
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
> Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at
> the same time.
>
> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux
On Tue, 8 Dec 2020 at 08:09, Krzysztof Kozlowski wrote:
>
> On Tue, 8 Dec 2020 at 05:42, Joel Stanley wrote:
> >
> > On Tue, 8 Dec 2020 at 04:37, Quan Nguyen
> > wrote:
> > >
> > > The Mt. Jade BMC is an ASPEED AST2500-based BMC for the Mt. Jade
>
this patch adds clock control logic into the LPC
> SNOOP driver.
>
> Fixes: 3772e5da4454 ("drivers/misc: Aspeed LPC snoop output using misc
> chardev")
>
> Signed-off-by: Jae Hyun Yoo
> Signed-off-by: Vernon Mauery
> Signed-off-by: John Wang
Reviewed-by: Joel Stanley
A
On Tue, 8 Dec 2020 at 01:26, Andrew Jeffery wrote:
>
> Determined by scope measurements at speed.
>
> Signed-off-by: Andrew Jeffery
Reviewed-by: Joel Stanley
... assuming the bindings get acked.
> ---
> arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 +
> 1 file
On Tue, 8 Dec 2020 at 04:37, Quan Nguyen wrote:
>
> The Mt. Jade BMC is an ASPEED AST2500-based BMC for the Mt. Jade
> hardware reference platform with Ampere's Altra Processor Family.
>
> Reviewed-by: Andrew Jeffery
> Reviewed-by: Joel Stanley
> Signed-off-by: Quan
Hello Rob,
On Tue, 8 Dec 2020 at 04:37, Quan Nguyen wrote:
>
> Add "ampere" entry for Ampere Computing LLC: amperecomputing.com
>
> Reviewed-by: Andrew Jeffery
> Reviewed-by: Joel Stanley
> Signed-off-by: Quan Nguyen
> Signed-off-by: Phong Vo
> Signed-off
On Sat, 21 Nov 2020 at 18:55, Guenter Roeck wrote:
>
> On Fri, Nov 20, 2020 at 11:33:12AM +1030, Joel Stanley wrote:
> > Hi Guenter, here's v2 of this series on behalf of Eddie. I made the
> > change to the compatible string that we spoke about in v2, and I'm happy
> >
On Wed, 2 Dec 2020 at 05:16, John Wang wrote:
>
Can you add a note here about why we are adding these so it's clear is
a fix/enhancement?
Also add a Fixes line for both patches.
> Signed-off-by: John Wang
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi |
this patch adds clock control logic into the LPC
> SNOOP driver.
>
> Signed-off-by: Jae Hyun Yoo
> Signed-off-by: Vernon Mauery
> Signed-off-by: John Wang
Reviewed-by: Joel Stanley
Thanks for sending these John. It is an excellent idea to upstream
fixes that have been developed.
I
On Mon, 7 Dec 2020 at 09:01, Troy Lee wrote:
>
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee
Reviewed-by: Joel Stanley
On Tue, 1 Dec 2020 at 13:58, Mark Brown wrote:
>
> On Tue, 3 Nov 2020 15:21:58 +0800, Chin-Ting Kuo wrote:
> > This patch series aims to porting ASPEED FMC/SPI memory controller
> > driver with spi-mem interface. Adjust device tree setting of SPI NOR
> > flash in order to fit real AST2600 EVB and
On Wed, 2 Dec 2020 at 06:37, Troy Lee wrote:
>
> Adding Aspeed AST2600 edac node into common devicetree.
>
> Signed-off-by: Troy Lee
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/
On Wed, 2 Dec 2020 at 06:37, Troy Lee wrote:
>
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee
> ---
> Change since v1:
> 1. Removing SoC specific code
> 2. Changing numerical representation of memory sizing
> ---
> drivers/edac/Kconfig | 6 +--
>
On Wed, 2 Dec 2020 at 06:37, Troy Lee wrote:
>
> Adding Aspeed AST2400 and AST2600 binding for edac driver.
>
> Signed-off-by: Troy Lee
Acked-by: Joel Stanley
> ---
> .../devicetree/bindings/edac/aspeed-sdram-edac.txt | 9 ++---
> 1 file changed, 6 inser
peed: Fix GPI only function problem.")
> Cc: Billy Tsai
> Cc: Joel Stanley
> Signed-off-by: Andrew Jeffery
I didn't read all of the text, but the code change looks good. This
should go to stable as the offending commit was also added to stable.
Reviewed-by: Joel Stanley
Tested-by:
From: Eddie James
Add the P10 compatible string.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
---
Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation
From: Eddie James
The P10 OCC has a different SRAM address for the command and response
buffers. In addition, the SBE commands to access the SRAM have changed
format. Add versioning to the driver to handle these differences.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off
Hi Guenter, here's v2 of this series on behalf of Eddie. I made the
change to the compatible string that we spoke about in v2, and I'm happy
for these to go through the hwmon tree.
v1:
https://lore.kernel.org/linux-hwmon/20200501150833.5251-1-eaja...@linux.ibm.com/
The OCC in the P10 has a
From: Eddie James
The latest version of the On-Chip Controller (OCC) has a different
format for the temperature sensor data. Add a new temperature sensor
version to handle this data.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
---
drivers/hwmon/occ
From: Eddie James
There is nothing to prevent multiple commands being executed
simultaneously. Add a mutex to prevent this.
Fixes: 606397d67f41 ("fsi: Add ast2600 master driver")
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Reviewed-by: Milton Miller
Signed-off-by: Jo
P_EMERG to capture bad-path reboots.
>
> Signed-off-by: Andrew Jeffery
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
> b/ar
se 64MB for firmware memory")
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
> b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dt
P_EMERG to capture bad-path reboots.
>
> Signed-off-by: Andrew Jeffery
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
> b/a
potential conflicts when multiple devices (beind the switches) use
> the same device address.
>
> Signed-off-by: Tao Ren
Reviewed-by: Joel Stanley
I will apply for 5.11.
> ---
> .../boot/dts/aspeed-bmc-facebook-minipack.dts | 888 ++
> 1 file changed, 888 inserti
On Tue, 10 Nov 2020 at 07:22, wrote:
>
> From: Tao Ren
>
> Update "data0" partition's size from 8MB to 4MB to fix "partition data0
> extends beyond the end of device" warning at bootup time.
Thanks for testing :)
> Signed-off-by: Tao Ren
Reviewed-by
On Thu, 12 Nov 2020 at 03:18, Patrick Williams wrote:
>
> On Wed, Nov 11, 2020 at 11:34:10PM +, Joel Stanley wrote:
> > On Wed, 11 Nov 2020 at 23:23, wrote:
> > >
> > > From: Tao Ren
> > >
> > > The patch series adds the initial version of d
vice trees.
>
> Patch #2 simplfies Wedge40 device tree by using the common dtsi.
>
> Patch #3 simplfies Wedge100 device tree by using the common dtsi.
>
> Patch #4 adds the initial version of device tree for Facebook Galaxy100
> BMC.
Nice. They look good to me.
Reviewed-by: Jo
On Wed, 11 Nov 2020 at 22:44, Supreeth Venkatesh
wrote:
>
>
>
> On 11/11/20 7:21 AM, Konstantin Aladyshev wrote:
> > [CAUTION: External Email]
> >
> > Add GPIO line names for AMD EthanolX customer reference board.
> > It populates AST2500 GPIO lines (A0-A7 to AC0-AC7) with AMD EthanolX
> >
t by finalizing the transfer in this
> case.
>
> Fixes: 9211a441e606 ("spi: fsi: Check mux status before transfers")
> Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
> ---
> drivers/spi/spi-fsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Thu, 5 Nov 2020 at 19:24, Pavel Machek wrote:
>
> Hi!
>
> > From: Joel Stanley
> >
> > commit a02f6d42357acf6e5de6ffc728e6e77faf3ad217 upstream.
> >
> > It's not done anything for a long time. Save the percpu variable, and
> > emit a warning to
On Thu, 13 Aug 2020 at 19:04, Vijay Khemka wrote:
>
> Removed vuart for facebook tiogapass platform as it uses uart2 and
> uart3 pin with aspeed uart routing feature.
>
> Signed-off-by: Vijay Khemka
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-faceb
On Sun, 1 Nov 2020 at 15:06, wrote:
>
> From: Tom Rix
>
> A semicolon is not needed after a switch statement.
Thanks Tom. I will add this to the aspeed soc tree.
>
> Signed-off-by: Tom Rix
> ---
> drivers/soc/aspeed/aspeed-socinfo.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Fri, 30 Oct 2020 at 04:28, Andrew Jeffery wrote:
>
> Hi Billy,
>
> On Tue, 27 Oct 2020, at 19:14, Billy Tsai wrote:
> > Some gpio pin at aspeed soc is input only and the prefix name of these
> > pin is "GPI" only. This patch fine-tune the condition of GPIO check from
> > "GPIO" to "GPI".
> >
>
On Thu, 29 Oct 2020 at 06:28, Dylan Hung wrote:
>
> The HVI3C shall be a group of I3C function, not an independent function.
> Correct the function name from "HVI3C" to "I3C".
>
> Signed-off-by: Dylan Hung
Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes")
I have a few device
On Wed, 28 Oct 2020 at 05:25, Joel Stanley wrote:
>
> On Tue, 27 Oct 2020 at 12:38, Konstantin Aladyshev
> wrote:
> >
> > KCS nodes compatible property in the 'aspeed-g5.dtsi' file was
> > changed to use v2 binding in the commit fa4c8ec6feaa
> > ("ARM: dts:
On Mon, 26 Oct 2020 at 01:05, Andrew Jeffery wrote:
>
>
>
> On Mon, 12 Oct 2020, at 14:01, Billy Tsai wrote:
> > This patch is used to fix the memory range of gpio0
> >
> > Signed-off-by: Billy Tsai
>
> Reviewed-by: Andrew Jeffery
I've applied this with:
Fixes: 8dbcb5b709b9 ("ARM: dts:
On Mon, 12 Oct 2020 at 04:56, Billy Tsai wrote:
>
> Hi Joel,
>
> Thanks for the review.
>
> On 2020/10/12, 12:35 PM, Joel Stanley wrote:
>
> > On Mon, 12 Oct 2020 at 03:32, Billy Tsai
> wrote:
> > >
> > > This patch is used t
Thanks for the response Stephen. Sorry it's taken me a while to get back to you.
On Wed, 14 Oct 2020 at 17:16, Stephen Boyd wrote:
>
> Quoting Joel Stanley (2020-10-13 22:28:00)
> > On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> > >
> > > Quoting
On Mon, 12 Oct 2020 at 05:25, Billy Tsai wrote:
>
> Hi Joel,
>
> On 2020/10/8, 11:49 AM, Joel Stanley wrote:
>
> On Thu, 8 Oct 2020 at 01:51, Billy Tsai wrote:
> > >
> > > This patch is used to add sgpiom and sgpios nodes and add pinc
On Wed, 28 Oct 2020 at 09:00, Supreeth Venkatesh
wrote:
>
> These changes are already merged in
> https://github.com/openbmc/linux/blob/dev-5.8/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
> by Joel.
> Please abandon these changes.
That is the openbmc kernel tree, where we stage patches on
On Tue, 27 Oct 2020 at 12:41, Konstantin Aladyshev
wrote:
>
> Enable the USB 2.0 Virtual Hub Controller and
> the Video Engine with it's reserved memory region for the implementation
> of the iKVM functionality in the BMC.
>
> Signed-off-by: Konstantin Aladyshev
Reviewe
On Thu, 22 Oct 2020 at 07:41, Benjamin Herrenschmidt
wrote:
>
> On Wed, 2020-10-21 at 14:40 +0200, Arnd Bergmann wrote:
> > On Wed, Oct 21, 2020 at 12:39 PM Joel Stanley wrote:
> >
> > >
> > > diff --git a/drivers/net/ethernet/faraday/ftgmac100.c
> > &g
of /dev/ipmi-kcs* devices
> KCS node variables also need to be changed to use v2 binding.
>
> Signed-off-by: Konstantin Aladyshev
Fixes: 09f5f680707e ("ipmi: kcs: aspeed: Implement v2 bindings")
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dt
in Aladyshev
I don't have any docs on the platform so I'll wait for a review from
Supreeth before applying this one.
It's a correct use of the bindings:
Reviewed-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 5 +
> 1 file changed, 5 insertions(+)
>
On Mon, 26 Oct 2020 at 22:22, Benjamin Herrenschmidt
wrote:
>
> On Fri, 2020-10-23 at 13:08 +, Dylan Hung wrote:
> > The issue was found on our test chip (ast2600 version A0) which is
> > just for testing and won't be mass-produced. This HW bug has been
> > fixed on ast2600 A1 and later
On Wed, 21 Oct 2020 at 12:40, Arnd Bergmann wrote:
>
> On Wed, Oct 21, 2020 at 12:39 PM Joel Stanley wrote:
>
> >
> > diff --git a/drivers/net/ethernet/faraday/ftgmac100.c
> > b/drivers/net/ethernet/faraday/ftgmac100.c
> > index 331d4bdd4a67..15cdfeb135b0 1006
On Fri, 16 Oct 2020 at 04:36, Andrew Jeffery wrote:
>
> Reserve a 1.5MiB region of memory to record kmsg dumps, console and
> userspace message state into 16kiB ring-buffer slots. The sizing allows
> for up to 32 dumps to be captured and read out.
>
> Set max-reason to KMSG_DUMP_EMERG to capture
On Fri, 16 Oct 2020 at 04:36, Andrew Jeffery wrote:
>
> Hi,
>
> We're looking to improve our crash data capture for the BMC on some IBM
> platforms. This small series enables ramoops for Rainier and Tacoma.
>
> Please review.
Reviewed-by: Joel Stanley
>
> Andrew
>
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