On 7/16/19 2:35 PM, Sowjanya Komatineni wrote:
On 7/15/19 10:37 PM, Dmitry Osipenko wrote:
В Mon, 15 Jul 2019 21:37:09 -0700
Sowjanya Komatineni пишет:
On 7/15/19 8:50 PM, Dmitry Osipenko wrote:
16.07.2019 6:00, Sowjanya Komatineni пишет:
On 7/15/19 5:35 PM, Sowjanya Komatineni wrote:
On 4/2/19 10:46 PM, Thierry Reding wrote:
On Tue, Apr 02, 2019 at 11:02:34AM +0800, Joseph Lo wrote:
Since the clocksource framework has the support for suspend time
compensation. Re-work the driver to use that, so we can reduce the
duplicate code.
Suggested-by: Daniel Lezcano
Signed-off
Since the clocksource framework has the support for suspend time
compensation. Re-work the driver to use that, so we can reduce the
duplicate code.
Suggested-by: Daniel Lezcano
Signed-off-by: Joseph Lo
---
drivers/clocksource/timer-tegra20.c | 63 +
1 file changed
On 2/22/19 4:43 PM, Daniel Lezcano wrote:
On 21/02/2019 08:21, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across
CPU suspends in power down state.
Also convert the original driver to use timer-of API.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
Acked-by: Thierry Reding
Acked-by: Jon Hunter
---
v7:
* kconfig fix for 'depends on ARM || ARM64'
* move
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
Acked-by: Jon Hunter
---
v7:
* no change
v6:
* add ack tag from Jon.
v5:
* no change
v4:
* no change
v3
On 2/18/19 5:39 PM, Daniel Lezcano wrote:
On 18/02/2019 10:01, Joseph Lo wrote:
On 2/15/19 11:14 PM, Daniel Lezcano wrote:
On 01/02/2019 17:16, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device
On 2/15/19 11:14 PM, Daniel Lezcano wrote:
On 01/02/2019 17:16, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power
On 2/13/19 4:55 PM, Daniel Lezcano wrote:
On 08/02/2019 14:23, Joseph Lo wrote:
Hi Daniel & Thomas,
Do we have the chance to get this patch merged for K5.1?
Hi Jospeh,
sorry for the delay, I was overbooked these past two weeks.
Overall it looks ok but give me a couple of days to re
Hi Daniel & Thomas,
Do we have the chance to get this patch merged for K5.1?
Thanks,
Joseph
On 2/2/19 12:16 AM, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the A
On 2/2/19 9:38 PM, Dmitry Osipenko wrote:
02.02.2019 2:53, Joseph Lo пишет:
On 2/2/19 2:08 AM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11
On 2/2/19 9:30 PM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6
On 2/2/19 2:08 AM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
Acked-by: Jon Hunter
---
v6:
* add ack tag from Jon.
v5:
* no change
v4:
* no change
v3:
* no change
v2:
* list
CPU suspends in power down state.
Also convert the original driver to use timer-of API.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
Acked-by: Thierry Reding
Acked-by: Jon Hunter
---
v6:
* refine the timer defines
* add ack tag from Jon.
v5
On 2/1/19 11:43 PM, Jon Hunter wrote:
On 01/02/2019 14:39, Joseph Lo wrote:
On 2/1/19 8:44 PM, Jon Hunter wrote:
On 01/02/2019 03:36, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6:36, Joseph Lo пишет:
Add support for the Tegra210 timer that runs
On 2/1/19 8:44 PM, Jon Hunter wrote:
On 01/02/2019 03:36, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6:36, Joseph Lo пишет:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
---
v5:
* no change
v4:
* no change
v3:
* no change
v2:
* list all the interrupts that are supported by tegra210
CPU suspends in power down state.
Also convert the original driver to use timer-of API.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
Acked-by: Thierry Reding
---
v5:
* add ack tag from Thierry
v4:
* merge timer-tegra210.c in previous version
CPU suspends in power down state.
Also convert the original driver to use timer-of API.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
---
v4:
* merge timer-tegra210.c in previous version into timer-tegra20.c
v3:
* use timer-of API
v2:
* add
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
---
V4:
* no change
v3:
* no change
v2:
* list all the interrupts that are supported by tegra210 timers block
* add
On 1/29/19 6:29 PM, Thierry Reding wrote:
On Tue, Jan 29, 2019 at 10:41:55AM +0200, Peter De Schrijver wrote:
On Mon, Jan 28, 2019 at 04:09:08PM +0100, Thierry Reding wrote:
...
Up to here this is a duplicate of timer-tegra20.c. And a lot of
tegra210_timer_init() is the same as
CPU suspends in power down state.
Based on the work of Antti P Miettinen
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
---
v3:
* use timer-of API
v2:
* add error clean-up code
---
drivers/clocksource/Kconfig | 8 +
drivers
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
---
v3:
* no change
v2:
* list all the interrupts that are supported by tegra210 timers block
* add RB tag from Rob
On 1/28/19 11:09 PM, Thierry Reding wrote:
On Mon, Jan 28, 2019 at 05:18:11PM +0800, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't
Hi Daniel,
Thanks for your review.
On 1/28/19 9:00 PM, Daniel Lezcano wrote:
On 28/01/2019 10:18, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
Reviewed-by: Rob Herring
---
v2:
* list all the interrupts that are supported by tegra210 timers block
* add RB tag from Rob.
---
.../bindings
CPU suspends in power down state.
Based on the work of Antti P Miettinen
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
---
v2:
* add error clean-up code
---
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile
On 1/25/19 8:01 PM, Jon Hunter wrote:
On 25/01/2019 03:23, Joseph Lo wrote:
Hi Jon,
Thanks for reviewing.
On 1/24/19 6:30 PM, Jon Hunter wrote:
On 07/01/2019 03:28, Joseph Lo wrote:
The Tegra210 timer provides fourteen 29-bit timer counters and one
32-bit
timestamp counter. The TMRs run
On 1/24/19 7:09 PM, Jon Hunter wrote:
On 07/01/2019 03:28, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power
Hi Jon,
Thanks for reviewing.
On 1/24/19 6:30 PM, Jon Hunter wrote:
On 07/01/2019 03:28, Joseph Lo wrote:
The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
---
.../bindings/timer/nvidia,tegra210-timer.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation
CPU suspends in power down state.
Based on the work of Antti P Miettinen
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
---
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer
On 07/20/2016 09:22 AM, Rob Herring wrote:
On Tue, Jul 19, 2016 at 05:17:23PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU
On 07/20/2016 09:22 AM, Rob Herring wrote:
On Tue, Jul 19, 2016 at 05:17:23PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Sorry. Please allow me just update the binding patches of this series.
Want to make sure the binding is acceptable first.
Thanks.
Changes
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo
---
Sorry. Please allow me just update the binding patches of this series.
Want to make sure the binding is acceptable first.
Thanks.
Changes in V3:
- use two cells
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V3:
- s/mmio-ram/mmio-sram/
- revise the file path of the reference binding documents and header files
for more generic viem in different SW projects
Changes in V2:
-
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo
---
Changes in V3:
- s/mmio-ram/mmio-sram/
- revise the file path of the reference binding documents and header files
for more generic viem in different SW projects
Changes in V2:
- update the message
On 07/19/2016 07:13 AM, Stephen Warren wrote:
On 07/11/2016 10:08 AM, Stephen Warren wrote:
On 07/11/2016 08:14 AM, Rob Herring wrote:
On Thu, Jul 07, 2016 at 12:35:02PM -0600, Stephen Warren wrote:
On 07/07/2016 12:13 PM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:22PM +0800, Joseph
On 07/19/2016 07:13 AM, Stephen Warren wrote:
On 07/11/2016 10:08 AM, Stephen Warren wrote:
On 07/11/2016 08:14 AM, Rob Herring wrote:
On Thu, Jul 07, 2016 at 12:35:02PM -0600, Stephen Warren wrote:
On 07/07/2016 12:13 PM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:22PM +0800, Joseph
On 07/08/2016 05:33 AM, Sivaram Nair wrote:
On Thu, Jul 07, 2016 at 02:37:27PM +0800, Joseph Lo wrote:
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo <jose...@nvidia.com> wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5
On 07/08/2016 05:33 AM, Sivaram Nair wrote:
On Thu, Jul 07, 2016 at 02:37:27PM +0800, Joseph Lo wrote:
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph
On 07/08/2016 05:10 AM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:23PM +0800, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules support some different features
On 07/08/2016 05:10 AM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:23PM +0800, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules support some different features
Hi Rob,
Thanks for your reviewing.
On 07/12/2016 12:05 AM, Stephen Warren wrote:
On 07/11/2016 08:22 AM, Rob Herring wrote:
On Tue, Jul 05, 2016 at 05:04:24PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading
Hi Rob,
Thanks for your reviewing.
On 07/12/2016 12:05 AM, Stephen Warren wrote:
On 07/11/2016 08:22 AM, Rob Herring wrote:
On Tue, Jul 05, 2016 at 05:04:24PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading
On 07/14/2016 03:41 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
On 07/14/2016 03:41 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
On 07/06/2016 07:39 PM, Alexandre Courbot wrote:
Sorry, I will probably need to do several passes on this one to
understand everything, but here is what I can say after a first look:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <jose...@nvidia.com> wrote:
The Tegra BPMP (Boot and Power Mana
On 07/06/2016 07:39 PM, Alexandre Courbot wrote:
Sorry, I will probably need to do several passes on this one to
understand everything, but here is what I can say after a first look:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra BPMP (Boot and Power Management Processor
On 07/07/2016 12:50 AM, Stephen Warren wrote:
On 07/06/2016 03:06 AM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <jose...@nvidia.com> wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interpro
On 07/07/2016 12:50 AM, Stephen Warren wrote:
On 07/06/2016 03:06 AM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo <jose...@nvidia.com> wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <jose...@nvidia.com> wrote:
The Tegra HSP mailbox driver implements t
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor
On 07/07/2016 01:03 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
On 07/07/2016 01:03 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
On 07/06/2016 07:42 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <jose...@nvidia.com> wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control
On 07/06/2016 07:42 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU
On 07/07/2016 01:02 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
On 07/07/2016 01:02 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <jose...@nvidia.com> wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules suppor
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules support some different features
.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- None
---
drivers/soc/tegra/Kconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 03089ad2fc65..88a71dfd466c 100644
--- a/drivers/soc/tegra/K
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair <sivar...@nvidia.com>
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- None
---
driv
.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/soc/tegra/Kconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 03089ad2fc65..88a71dfd466c 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/firmware/tegra/Kconfig | 12 +
drivers/firmware
and payloads. So the
clients can use it to send/receive messages to/from remote ones.
We introduce it as a library for the firmware drivers, which can use it
for IPC.
Based-on-the-work-by:
Peter Newman <pnew...@nvidia.com>
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes i
Enable Tegra186 SoC.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- None
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e69051098435..64d767ec142c 100644
--- a/arch
and payloads. So the
clients can use it to send/receive messages to/from remote ones.
We introduce it as a library for the firmware drivers, which can use it
for IPC.
Based-on-the-work-by:
Peter Newman
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/firmware/Kconfig| 1
Enable Tegra186 SoC.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e69051098435..64d767ec142c 100644
--- a/arch/arm64/configs/defconfig
This adds the initial support of Tegra186 SoC, which can help to bring
up the debug console and initrd for further developing.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- update the file according the HSP and BPMP binding fix in V2
---
arch/arm64/boot/dts/nvidia/te
This adds the initial support of Tegra186 SoC, which can help to bring
up the debug console and initrd for further developing.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update the file according the HSP and BPMP binding fix in V2
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 77
. And there are multiple HSP HW instances on the chip. So the
driver is extendable to support more features for different IPC
requirement.
The driver of remote processor can use it as a mailbox client and deal
with the IPC protocol to synchronize the data communications.
Signed-off-by: Joseph Lo <j
Add NVIDIA Tegra186 P3310 main board support, which is a chip module
with DRAM, nonvolatile storage, WiFi, ethernet and PMIC chips on it. It
also needs an IO board and hooks on it to represent as an application
platform.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
-
Add NVIDIA Tegra186 P2771 board support, which is a reference
development board with P2597 I/O board and P3310 chip module on it.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- None
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/
Add NVIDIA Tegra186 P3310 main board support, which is a chip module
with DRAM, nonvolatile storage, WiFi, ethernet and PMIC chips on it. It
also needs an IO board and hooks on it to represent as an application
platform.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update according
Add NVIDIA Tegra186 P2771 board support, which is a reference
development board with P2597 I/O board and P3310 chip module on it.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
. And there are multiple HSP HW instances on the chip. So the
driver is extendable to support more features for different IPC
requirement.
The driver of remote processor can use it as a mailbox client and deal
with the IPC protocol to synchronize the data communications.
Signed-off-by: Joseph Lo
---
Changes in V2
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- update the message that the BPMP is clock and reset control provider
- add tegra186-clock.h and tegra186-reset.h header files
- revise the description of the re
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update the message that the BPMP is clock and reset control provider
- add tegra186-clock.h and tegra186-reset.h header files
- revise the description of the required properties
to represent the binding update
Joseph Lo (10):
Documentation: dt-bindings: mailbox: tegra: Add binding for HSP
mailbox
mailbox: tegra-hsp: Add HSP(Hardware Synchronization Primitives)
driver
Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP
firmware: tegra: add
to represent the binding update
Joseph Lo (10):
Documentation: dt-bindings: mailbox: tegra: Add binding for HSP
mailbox
mailbox: tegra-hsp: Add HSP(Hardware Synchronization Primitives)
driver
Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP
firmware: tegra: add
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
Changes in V2:
- revise the compatible string, interrupt-names, interrupts, and #mbox-cells
properties
- remove "nvidia,hsp-functio
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo
---
Changes in V2:
- revise the compatible string, interrupt-names, interrupts, and #mbox-cells
properties
- remove "nvidia,hsp-function" property
- fix
On 07/01/2016 12:02 AM, Stephen Warren wrote:
On 06/30/2016 03:25 AM, Joseph Lo wrote:
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM
On 07/01/2016 12:02 AM, Stephen Warren wrote:
On 06/30/2016 03:25 AM, Joseph Lo wrote:
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage of HSP HW in the downstream kernel is something like
the model below.
remote_processor_A
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage of HSP HW in the downstream kernel is something like
the model below.
remote_processor_A
On 06/28/2016 12:08 AM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management tasks
from the CPU. The binding document defines the resources that would
On 06/28/2016 12:08 AM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management tasks
from the CPU. The binding document defines the resources that would
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair <sivar...@nvidia.com>
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
drivers/firmware/tegra/Kco
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair
Signed-off-by: Joseph Lo
---
drivers/firmware/tegra/Kconfig | 12 +
drivers/firmware/tegra/Makefile |1
.
Signed-off-by: Joseph Lo <jose...@nvidia.com>
---
drivers/soc/tegra/Kconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 03089ad2fc65..88a71dfd466c 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc
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