Hi Jonathan,
On 2021/04/12 17:42, Jonathan Cameron wrote:
On Sat, 10 Apr 2021 01:22:16 +0900
Kunihiko Hayashi wrote:
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Trivial comment inline.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko
associated
with Root Port, and returns its vIRQ number.
Cc: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 101 +
1 file changed, 89
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
Acked-by: Bjorn Helgaas
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
PCI: portdrv: Add pcie_port_service_get_irq() function
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to invoke PME and AER
Gentle Ping.
Are there any comments about these two patches?
Thank you,
On Tue, 9 Mar 2021 09:37:15 +0900
Kunihiko Hayashi wrote:
> After applying the commit bbc4d71d6354
> ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the configuration
> register for TXDLY and RXD
anges 'phy-mode' property
to 'rgmii-id' as default.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi
b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 4d9f69a..5ba8
anges 'phy-mode' property
to 'rgmii-id' as default.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/socionex
On Tue, 2 Mar 2021 15:20:08 -0500
Konrad Rzeszutek Wilk wrote:
> On 3/2/21 12:21 PM, Kunihiko Hayashi wrote:
> > After the refactoring phase, the type of max_slot has changed from unsigned
> > long to unsigned int. The return type of the function get_max_slots() and
> >
: Christoph Hellwig
Fixes: 567d877f9a7d ("swiotlb: refactor swiotlb_tbl_map_single")
Signed-off-by: Kunihiko Hayashi
---
kernel/dma/swiotlb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 369e4c3..c10e855 100644
--
tps://patchwork.kernel.org/project/linux-pci/patch/20210125044803.4310-1-zhiqiang@nxp.com/
On 2021/01/21 0:20, Rob Herring wrote:
On Mon, Jan 18, 2021 at 5:10 PM Kunihiko Hayashi
wrote:
The commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows") gets
the values of pci->num_ib
Hi Kishon,
On 2021/01/28 23:11, Kishon Vijay Abraham I wrote:
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
This adds a member 'started' as a boolean value to struct pci_epc to set
whether the controller is started, and also adds a function to get the
value.
Signed-off
Hi Kishon,
Thank you for your comment.
On 2021/01/28 23:29, Kishon Vijay Abraham I wrote:
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
Set the polling function and call the init function to enable EPC restart
management. The polling function detects that the bus-reset signal
that your patch move
some of the software perspective initializations into hardware ones.
Ok, I checked your patch fixed this issue on my board with or without
my patch. I'll follow the maintainers for handling my patch.
Tested-by: Kunihiko Hayashi
Thank you,
Thanks
Zhiqiang
-Original
struct dw_pcie *pci);
+void dw_pcie_iatu_detect(struct dw_pcie *pci);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{
---
Best Regards
Kunihiko Hayashi
Set the polling function and call the init function to enable EPC restart
management. The polling function detects that the bus-reset signal is a
rising edge.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig| 1 +
drivers/pci/controller/dwc/pcie-uniphier-ep.c
it. The configuration
paremters are restored to the user's values.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/Kconfig | 9 +++
drivers/pci/endpoint/Makefile | 1 +
drivers/pci/endpoint/pci-epc-restart.c | 114 +
include/linux/pci-epc.h
This adds a member 'started' as a boolean value to struct pci_epc to set
whether the controller is started, and also adds a function to get the
value.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/pci-epc-core.c | 2 ++
include/linux/pci-epc.h | 7 +++
2 files changed
the endpoint controller.
This series is only for UniPhier PCIe endpoint controller at this point.
Changes since v1:
- Update the patches to rebase onto the latest tree
Kunihiko Hayashi (3):
PCI: endpoint: Add 'started' to pci_epc to set whether the controller
is started
PCI: endpoint: Add
hould be referenced after they are set by
dw_pcie_iatu_detect_regions*() called from dw_pcie_setup().
Cc: Rob Herring
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 41
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
associated
with Root Port, and returns its vIRQ number.
Cc: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 101 +
1 file changed, 89
OBE_DEFER
- Fix iATU register mapping method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
Acked-by: Bjorn Helgaas
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
es of window_map. It's necessary to refer
the values after they are set in dw_pcie_setup().
Cc: Rob Herring
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 41 ---
Hi Bjorn Lorenzo,
On 2020/11/25 19:23, Lorenzo Pieralisi wrote:
On Tue, Nov 24, 2020 at 05:20:37PM -0600, Bjorn Helgaas wrote:
On Wed, Oct 28, 2020 at 10:31:43AM +0900, Kunihiko Hayashi wrote:
This patch adds misc interrupt handler to detect and invoke PME/AER event.
In UniPhier PCIe
init_new_context(struct task_struct *tsk,
| ^~~~
Cc: Nicholas Piggin
Fixes: 4c792ad103f3 ("arm64: use asm-generic/mmu_context.h for no-op
implementations")
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/include/asm/mmu_context.h | 1 +
1 file
Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci
d printing phy error message in case of EPROBE_DEFER
- Fix iATU register mapping method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
Hi,
Gentle ping.
Are there any comments about this series?
Thank you,
On 2020/09/11 18:33, Kunihiko Hayashi wrote:
The original subject up to v6 is
"PCI: uniphier: Add features for UniPhier PCIe host controller".
This adds a new function called by MSI handler in DesignWare PCIe
it. The configuration
paremters are restored to the user's values.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/Kconfig | 9 +++
drivers/pci/endpoint/Makefile | 1 +
drivers/pci/endpoint/pci-epc-restart.c | 114 +
include/linux/pci-epc.h
the endpoint controller.
This series is only for UniPhier PCIe endpoint controller at this point.
Kunihiko Hayashi (3):
PCI: endpoint: Add 'started' to pci_epc to set whether the controller
is started
PCI: endpoint: Add endpoint restart management
PCI: uniphier-ep: Add EPC restart management
Set the polling function and call the init function to enable EPC restart
management. The polling function detects that the bus-reset signal is a
rising edge.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig| 1 +
drivers/pci/controller/dwc/pcie-uniphier-ep.c
This adds a member 'started' as a boolean value to struct pci_epc to set
whether the controller is started, and also adds a function to get the
value.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/endpoint/pci-epc-core.c | 2 ++
include/linux/pci-epc.h | 7 +++
2 files changed
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
---
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 20 ++--
1 file changed, 14 insertions(+), 6 deletion
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 3fe859f..b6b39af 100644
--- a/d
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
d
ck
Changes since v1:
- Use to_platform_device() instead of of_find_device_by_node()
- Add Reviewed-by: line to 4th patch for keystone
- dt-bindings: Add description for uniphier-ep
Kunihiko Hayashi (4):
dt-bindings: PCI: uniphier: Add iATU register description
dt-bindings: PCI: uniphier-e
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
On 2020/09/29 3:09, Rob Herring wrote:
On Mon, 28 Sep 2020 10:05:31 +0900, Kunihiko Hayashi wrote:
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetre
Use devm_alloc_etherdev() to simplify the code instead of alloc_etherdev().
Signed-off-by: Kunihiko Hayashi
---
drivers/net/ethernet/socionext/sni_ave.c | 32 +++-
1 file changed, 11 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/socionext
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 3fe859f..b6b39af 100644
--- a/d
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
---
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
d
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
vice_by_node()
- Add Reviewed-by: line to 4th patch for keystone
- dt-bindings: Add description for uniphier-ep
Kunihiko Hayashi (4):
dt-bindings: PCI: uniphier: Add iATU register description
dt-bindings: PCI: uniphier-ep: Add iATU register description
PCI: dwc: Add common iATU register sup
On 2020/09/25 18:10, Kunihiko Hayashi wrote:
Hi Rob,
On 2020/09/24 0:57, Rob Herring wrote:
On Fri, Sep 11, 2020 at 05:50:02PM +0900, Kunihiko Hayashi wrote:
This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iAT
Hi Rob,
On 2020/09/24 0:57, Rob Herring wrote:
On Fri, Sep 11, 2020 at 05:50:02PM +0900, Kunihiko Hayashi wrote:
This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iATU register area is
separated from core reg
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
Reviewed-by: Rob Herring
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff
method
- dt-bindings: Add Acked-by: line
- Fix typos in commit messages
- Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (3):
PCI: portdrv: Add pcie_port_service_get_irq() func
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed, 17 insertions(+)
diff
Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniphier.c
;iatu" property description to the dt-bindings
for UniPhier PCIe host controller.
This has been confirmed with PCIe version 4.80 controller on UniPhier platform.
Please test this series on Keystone platform.
Kunihiko Hayashi (3):
dt-bindings: PCI: uniphier: Add iATU register description
PCI:
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-designware.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 4d105ef..4a36
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Cc: Murali Karicheri
Cc: Jingoo Han
Cc: Gustavo Pimentel
Suggested-by: Rob Herring
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pci-keyst
Hi Rob,
On 2020/09/04 7:25, Rob Herring wrote:
On Fri, Aug 21, 2020 at 1:05 AM Kunihiko Hayashi
wrote:
On 2020/08/18 1:39, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
Even if phy driver doesn't probe, the error message can't be distinguished
from other
Hi Rob,
On 2020/09/04 7:12, Rob Herring wrote:
On Fri, Aug 21, 2020 at 1:05 AM Kunihiko Hayashi
wrote:
On 2020/08/18 1:48, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later
Hi John,
On 2020/08/22 3:32, John Stultz wrote:
On Fri, Aug 21, 2020 at 2:14 AM Kunihiko Hayashi
wrote:
On 2020/08/01 4:38, John Stultz wrote:
On Fri, Jul 31, 2020 at 2:32 AM Kunihiko Hayashi
wrote:
On 2020/07/29 4:17, John Stultz wrote:
Do you have a upstream driver that you plan
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
the controller
- Remove redundant .init in uniphier_pxs2_data
- Add comments for dummy read accesses
- Fix return value in uniphier_ahciphy_init
- dt-bindings: Add Reviewed-by line
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY
Hi Vinod,
On 2020/08/23 22:26, Vinod Koul wrote:
Hello,
On 21-08-20, 18:20, Kunihiko Hayashi wrote:
Gentle ping.
Are there any comments in this series?
Sorry I dont have this in my inbox, can you please rebease and resend to
me as well
Okay, No problem. I confirmed that rebasing
Gentle ping.
Are there any comments in this series?
Thank you,
On 2020/07/16 17:32, Kunihiko Hayashi wrote:
This series adds support for AHCI PHY interface implemented in Socionext
UniPhier SoCs. This driver supports PXs2 and PXs3 SoCs.
Changes since v3:
- Eliminate a meaningless blank line
On 2020/08/01 4:38, John Stultz wrote:
On Fri, Jul 31, 2020 at 2:32 AM Kunihiko Hayashi
wrote:
On 2020/07/29 4:17, John Stultz wrote:
Do you have a upstream driver that you plan to make use this new call?
Unfortunately I don't have an upstream driver using this call.
This call is called
On 2020/08/18 1:48, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT
On 2020/08/18 1:39, Rob Herring wrote:
On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi
wrote:
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihiko Hayashi
Use devm_platform_ioremap_resource_byname()
Changes since v1:
- Add check if struct resource is NULL
- Fix warning in the type of dev_err() argument
Kunihiko Hayashi (6):
PCI: portdrv: Add pcie_port_service_get_irq() function
PCI: dwc: Add msi_host_isr() callback
PCI: uniphier: Add misc interrupt handler to inv
Pimentel
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +-
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniphier.c
This gets iATU register area from reg property. In Synopsys DWC version
4.80 or later, since iATU register area is separated from core register
area, this area is necessary to get from DT independently.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 5 +
1
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16
2 files changed, 17 insertions(+)
diff
In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.
Signed-off-by: Kunihiko Hayashi
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
1 file changed, 1 insertion(+)
Even if phy driver doesn't probe, the error message can't be distinguished
from other errors. This displays error message caused by the phy driver
explicitly.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++--
1 file changed, 6 insertions(+), 2
: Marc Zyngier
Cc: Jingoo Han
Cc: Gustavo Pimentel
Signed-off-by: Kunihiko Hayashi
Acked-by: Gustavo Pimentel
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci
On 2020/07/15 19:04, Kunihiko Hayashi wrote:
Hi Lorenzo,
On 2020/07/14 22:27, Lorenzo Pieralisi wrote:
On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx handler, however, these interrupts should
Hi John,
Thank you for your comment.
On 2020/07/29 4:17, John Stultz wrote:
On Thu, Jul 16, 2020 at 6:10 PM Kunihiko Hayashi
wrote:
Current dma-buf heaps can handle only default CMA. This introduces
dma_heap_add_cma() function to attach CMA heaps that belongs to a device.
At first
nmode_mask, priv->pinmode_val);
if (ret)
- return ret;
+ goto out_reset_assert;
ave_global_reset(ndev);
Thank you for pointing out.
Reviewed-by: Kunihiko Hayashi
---
Best Regards
Kunihiko Hayashi
ociated with the CMA become available as dma-buf heaps.
Signed-off-by: Kunihiko Hayashi
---
drivers/dma-buf/heaps/cma_heap.c | 12
include/linux/dma-heap.h | 9 +
2 files changed, 21 insertions(+)
diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/he
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
the controller
- Remove redundant .init in uniphier_pxs2_data
- Add comments for dummy read accesses
- Fix return value in uniphier_ahciphy_init
- dt-bindings: Add Reviewed-by line
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Hi Vinod,
On 2020/07/16 15:37, Vinod Koul wrote:
On 16-07-20, 11:43, Kunihiko Hayashi wrote:
+static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
+{
+ int i;
+ u32 val;
+
+ /* setup port parameter */
+ val = readl(priv->base + TXCT
- Fix return value in uniphier_ahciphy_init
- dt-bindings: Add Reviewed-by line
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY description
phy: socionext: Add UniPhier AHCI PHY driver support
.../bindings/phy/socionext
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Rob Herring
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
Hi Lorenzo,
On 2020/07/14 22:27, Lorenzo Pieralisi wrote:
On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx handler, however, these interrupts should be also handled by
MSI handler.
Define what you
Hi Lorenzo,
On 2020/07/11 1:14, Lorenzo Pieralisi wrote:
On Wed, Jul 01, 2020 at 11:18:29AM +0900, Kunihiko Hayashi wrote:
[...]
-static void uniphier_pcie_irq_handler(struct irq_desc *desc)
+static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi)
{
- struct pcie_port
Hi Vinod,
On 2020/07/13 14:05, Vinod Koul wrote:
On 30-06-20, 17:59, Kunihiko Hayashi wrote:
+++ b/drivers/phy/socionext/phy-uniphier-ahci.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller
+ * Copyright 2016-2018
to pci/dwc and resend this series without 6/6?
Thank you,
On 2020/06/18 17:38, Kunihiko Hayashi wrote:
Use devm_platform_ioremap_resource_byname() to simplify the code a bit.
Signed-off-by: Kunihiko Hayashi f
---
drivers/pci/controller/dwc/pcie-uniphier.c | 3 +--
1 file changed, 1 insertion
The usb3-hsphy for PXs3 SoC needs to accept 3 clocks like usb3-ssphy.
Fixes: 134ab2845acb ("dt-bindings: phy: Convert UniPhier USB3-PHY conroller to
json-schema")
Signed-off-by: Kunihiko Hayashi
---
.../devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml| 8 ++--
1 fi
This adds missing clock-names and reset-names to pcie-phy node according to
Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++
2
This renames the node name "ethphy" to "ethernet-phy" according to
Documentation/devicetree/bindings/net/mdio.yaml.
Signed-off-by: Kunihiko Hayashi
---
arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts | 2
This renames the node name "ethphy" to "ethernet-phy" according to
Documentation/devicetree/bindings/net/mdio.yaml.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-ld6b-ref.dts| 2 +-
arch/arm/boot/dts/uniphier-pro4-ace.dts| 2 +-
arch/arm/boot/dts/u
This adds PCIe endpoint controller and PHY nodes for Pro5 SoC,
and also adds pinctrl node for PCIe.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/boot/dts/uniphier-pinctrl.dtsi | 5 +
arch/arm/boot/dts/uniphier-pro5.dtsi| 30 ++
2 files changed, 35 insertions
Hi Marc,
On 2020/06/30 22:23, Marc Zyngier wrote:
On 2020-06-29 10:49, Kunihiko Hayashi wrote:
Hi Marc,
On 2020/06/27 18:48, Marc Zyngier wrote:
On Thu, 18 Jun 2020 09:38:09 +0100,
Kunihiko Hayashi wrote:
The misc interrupts consisting of PME, AER, and Link event, is handled
by INTx
Add a driver for PHY interface built into ahci controller implemented
in UniPhier SoCs. This supports PXs2 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi
---
drivers/phy/socionext/Kconfig | 10 +
drivers/phy/socionext/Makefile| 1 +
drivers/phy/socionext/phy-uniphier
This series adds support for AHCI PHY interface implemented in Socionext
UniPhier SoCs. This driver supports PXs2 and PXs3 SoCs.
Changes since v1:
- dt-bindings: Fix items in reset-names
Kunihiko Hayashi (2):
dt-bindings: phy: Add UniPhier AHCI PHY description
phy: socionext: Add UniPhier
Add DT bindings for PHY interface built into ahci controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi
---
.../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Documentation/devicetree/bindings
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