Re: [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

2021-04-14 Thread Like Xu
On 2021/4/15 10:49, Liuxiangdong wrote: On 2021/4/15 9:38, Xu, Like wrote: On 2021/4/14 22:49, Liuxiangdong wrote: Hi Like, On 2021/4/9 16:46, Like Xu wrote: Hi Liuxiangdong, On 2021/4/9 16:33, Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.) wrote: Do you have any

[PATCH v5 16/16] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64

2021-04-14 Thread Like Xu
: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 26 ++ arch/x86/kvm/vmx/vmx.c | 15 +++ 2 files changed, 33 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx

[PATCH v5 15/16] KVM: x86/cpuid: Refactor host/guest CPU model consistency check

2021-04-14 Thread Like Xu
For the same purpose, the leagcy intel_pmu_lbr_is_compatible() can be renamed for reuse by more callers, and remove the comment about LBR use case can be deleted by the way. Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.h | 5 + arch/x86/kvm/vmx/pmu_intel.c | 12 +--- arch

[PATCH v5 14/16] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability

2021-04-14 Thread Like Xu
The information obtained from the interface perf_get_x86_pmu_capability() doesn't change, so an exportable "struct x86_pmu_capability" is introduced for all guests in the KVM, and it's initialized before hardware_setup(). Signed-off-by: Like Xu --- arch/x86/kvm/

[PATCH v5 13/16] KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations

2021-04-14 Thread Like Xu
r are still accurate and the above two restrictions will be checked before each vm-entry only if guest PEBS is deemed to be enabled. Suggested-by: Wei Wang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c| 11 +-- arch/x86/include/asm/kvm_host.h | 9 + arch/x86/kv

[PATCH v5 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled

2021-04-14 Thread Like Xu
ned-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ arch/x86/kvm/x86.c | 4 2 files changed, 6 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 58f32a55cc2e..c846d3eef7a7 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x

[PATCH v5 11/16] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter

2021-04-14 Thread Like Xu
. The cpu model check is also required since some platforms may place the PEBS-PDIR facility in another counter index. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 2 ++ arch/x86/kvm/pmu.h | 7 +++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index

[PATCH v5 12/16] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h

2021-04-14 Thread Like Xu
It allows this inline function to be reused by more callers in more files, such as pmu_intel.c. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 11 --- arch/x86/kvm/pmu.h | 11 +++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm

[PATCH v5 09/16] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS

2021-04-14 Thread Like Xu
guest adaptive PEBS is enabled, the IA32_PEBS_ENABLE MSR will be added to the perf_guest_switch_msr() and switched during the VMX transitions just like CORE_PERF_GLOBAL_CTRL MSR. Co-developed-by: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c

[PATCH v5 08/16] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS

2021-04-14 Thread Like Xu
switched during the VMX transitions just like CORE_PERF_GLOBAL_CTRL MSR. The WRMSR to IA32_DS_AREA MSR brings a #GP(0) if the source register contains a non-canonical address. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events

[PATCH v5 06/16] KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter

2021-04-14 Thread Like Xu
overflow PMI based on guest IA32_DS_AREA MSR. Even with the same counter index and the same event code and mask, guest PEBS events will not be reused for non-PEBS events. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/kvm

[PATCH v5 07/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS

2021-04-14 Thread Like Xu
x86_pmu.pebs_vmx, it has also refactored the way to add more msrs to art[] in intel_guest_get_msrs() for extensibility. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Co-developed-by: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86

[PATCH v5 05/16] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter

2021-04-14 Thread Like Xu
Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c| 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 44f893043a3c..5b9692397350

[PATCH v5 02/16] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest

2021-04-14 Thread Like Xu
rom its own PEBS records buffer. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c | 40 1 file changed, 40 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/

[PATCH v5 04/16] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled

2021-04-14 Thread Like Xu
On Intel platforms, the software can use the IA32_MISC_ENABLE[7] bit to detect whether the processor supports performance monitoring facility. It depends on the PMU is enabled for the guest, and a software write operation to this available bit will be ignored. Cc: Yao Yuan Signed-off-by: Like

[PATCH v5 03/16] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values

2021-04-14 Thread Like Xu
d-off-by: Like Xu --- arch/x86/events/core.c| 4 ++-- arch/x86/events/intel/core.c | 4 ++-- arch/x86/events/perf_event.h | 2 +- arch/x86/include/asm/perf_event.h | 4 ++-- arch/x86/kvm/vmx/vmx.c| 3 ++- 5 files changed, 9 insertions(+), 8 deletions(-) diff --

[PATCH v5 01/16] perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server

2021-04-14 Thread Like Xu
guest. Signed-off-by: Like Xu --- arch/x86/events/core.c| 1 + arch/x86/events/intel/core.c | 1 + arch/x86/events/perf_event.h | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86

[PATCH v5 00/16] KVM: x86/pmu: Add basic support to enable guest PEBS via DS

2021-04-14 Thread Like Xu
stfloor.org/ v4->v5 Changelog: - Rewrite intel_guest_get_msrs() to address Peter's comments; - Fix coding style including indentation and {}; - Use __test_and_set_bit in the kvm_perf_overflow_intr(); - Return void for x86_pmu_handle_guest_pebs(); - Always drain pebs buffer on the host sid

Re: [PATCH v5 0/5] perf/x86: Some minor changes to support guest Arch LBR

2021-04-09 Thread Like Xu
Em, does anyone want to review these minor changes? I believe some of them solve the real problem. On 2021/4/6 11:20, Like Xu wrote: Hi all, do we have any comments on this patch set? On 2021/3/26 9:19, Like Xu wrote: Hi Peter, Please help review these minor perf/x86 changes in this patch

Re: [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

2021-04-09 Thread Like Xu
Hi Liuxiangdong, On 2021/4/9 16:33, Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.) wrote: Do you have any comments or ideas about it ? https://lore.kernel.org/kvm/606e5ef6.2060...@huawei.com/ My expectation is that there may be many fewer PEBS samples on Skylake without any

Re: [PATCH v5 0/5] perf/x86: Some minor changes to support guest Arch LBR

2021-04-05 Thread Like Xu
Hi all, do we have any comments on this patch set? On 2021/3/26 9:19, Like Xu wrote: Hi Peter, Please help review these minor perf/x86 changes in this patch set, and we need some of them to support Guest Architectural LBR in KVM. This version keeps reserve_lbr_buffers() as is because the LBR

[PATCH v4 15/16] KVM: x86/cpuid: Refactor host/guest CPU model consistency check

2021-03-28 Thread Like Xu
For the same purpose, the leagcy intel_pmu_lbr_is_compatible() could be renamed for reuse by more callers for the same purpose and remove the comment about LBR use case incidentally. Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.h | 5 + arch/x86/kvm/vmx/pmu_intel.c | 12

[PATCH v4 16/16] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64

2021-03-28 Thread Like Xu
: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 26 -- arch/x86/kvm/vmx/vmx.c | 15 +++ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx

[PATCH v4 14/16] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability

2021-03-28 Thread Like Xu
The information obtained from the interface perf_get_x86_pmu_capability() doesn't change, so an exported "struct x86_pmu_capability" is introduced for all guests in the KVM, and it's initialized before hardware_setup(). Signed-off-by: Like Xu --- arch/x86/kvm/

[PATCH v4 12/16] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h

2021-03-28 Thread Like Xu
It allows this inline function to be reused by more callers in more files, such as pmu_intel.c. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 11 --- arch/x86/kvm/pmu.h | 11 +++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm

[PATCH v4 13/16] KVM: x86/pmu: Disable guest PEBS before vm-entry in two cases

2021-03-28 Thread Like Xu
still accurate and the above two restrictions will be checked before each vm-entry only if guest PEBS is deemed to be enabled. Signed-off-by: Like Xu --- arch/x86/events/intel/core.c| 8 +++- arch/x86/include/asm/kvm_host.h | 9 + arch/x86/kvm/vmx/pmu_intel.c

[PATCH v4 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled

2021-03-28 Thread Like Xu
ned-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ arch/x86/kvm/x86.c | 4 2 files changed, 6 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 7f18c760dbae..4dcf66e6c398 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x

[PATCH v4 09/16] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS

2021-03-28 Thread Like Xu
: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c| 11 ++- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/vmx/pmu_intel.c| 16 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel

[PATCH v4 11/16] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter

2021-03-28 Thread Like Xu
. The cpu model check is also required since some platforms may place the PEBS-PDIR facility in another counter index. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 2 ++ arch/x86/kvm/pmu.h | 7 +++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index

[PATCH v4 08/16] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to manage guest DS buffer

2021-03-28 Thread Like Xu
n Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c| 15 --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c| 11 +++ arch/x86/kvm/vmx/vmx.c | 1 + 4 files changed, 25 insertions(

[PATCH v4 06/16] KVM: x86/pmu: Reprogram guest PEBS event to emulate guest PEBS counter

2021-03-28 Thread Like Xu
guest counter index. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/pmu.c | 33 +++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff

[PATCH v4 05/16] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter

2021-03-28 Thread Like Xu
Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c| 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index a52f973bdff6..c560960544a3

[PATCH v4 07/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS

2021-03-28 Thread Like Xu
Liang Signed-off-by: Kan Liang Co-developed-by: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c | 17 + arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 6 ++ arch/x86/kvm/vmx/pmu_intel.c | 28

[PATCH v4 04/16] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled

2021-03-28 Thread Like Xu
On Intel platforms, software may uses IA32_MISC_ENABLE[7] bit to detect whether the performance monitoring facility is supported in the processor. It's dependent on the PMU being enabled for the guest and a write to this PMU available bit will be ignored. Cc: Yao Yuan Signed-off-by: Li

[PATCH v4 00/16] KVM: x86/pmu: Add basic support to enable Guest PEBS via DS

2021-03-28 Thread Like Xu
not set; - Make vmx_icl_pebs_cpu specific for PEBS-PDIR emulation; - Fix a bug for fixed_ctr_ctrl_mask; - Add two minor refactoring patches for reuse; Like Xu (16): perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest perf/x86

[PATCH v4 03/16] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values

2021-03-28 Thread Like Xu
d-off-by: Like Xu --- arch/x86/events/core.c| 4 ++-- arch/x86/events/intel/core.c | 4 ++-- arch/x86/events/perf_event.h | 2 +- arch/x86/include/asm/perf_event.h | 4 ++-- arch/x86/kvm/vmx/vmx.c| 3 ++- 5 files changed, 9 insertions(+), 8 deletions(-) diff --

[PATCH v4 02/16] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest

2021-03-28 Thread Like Xu
ion from its own PEBS records buffer. Originally-by: Andi Kleen Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c | 45 +++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/x86/eve

[PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

2021-03-28 Thread Like Xu
guest. Signed-off-by: Like Xu --- arch/x86/events/core.c| 1 + arch/x86/events/intel/core.c | 1 + arch/x86/events/perf_event.h | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86

[PATCH v5 4/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-25 Thread Like Xu
ed for each cpu like the legacy ds_buffer. Fixes: c085fb8774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read") Suggested-by: Kan Liang Tested-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/core.c | 8 +--- arch/x86/events/intel/bts.c | 2 +- arc

[PATCH v5 3/5] perf/x86: Skip checking MSR for MSR 0x000

2021-03-25 Thread Like Xu
hitectural LBR") Signed-off-by: Like Xu Reviewed-by: Kan Liang --- arch/x86/events/intel/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 382dd3994463..564c9851dd34 100644 --- a/arch/x86/even

[PATCH v5 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-03-25 Thread Like Xu
The x86_pmu.lbr_info is 0 unless explicitly initialized, so there's no point checking x86_pmu.intel_cap.lbr_format. Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a

[PATCH v5 5/5] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h

2021-03-25 Thread Like Xu
The ARCH_LBR_CTL_MASK will be reused for LBR emulation in the KVM. Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 2 -- arch/x86/include/asm/msr-index.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c

[PATCH v5 0/5] perf/x86: Some minor changes to support guest Arch LBR

2021-03-25 Thread Like Xu
/20210322060635.821531-1-like...@linux.intel.com/ v4->v5 Changelog: - Add "Tested-by: Kan Liang" - Make the commit message simpler - Make check_msr() to ignore msr==0 - Use kmem_cache_alloc_node() [Namhyung] Like Xu (5): perf/x86/intel: Fix the comment about guest LBR support on KVM

[PATCH v5 1/5] perf/x86/intel: Fix the comment about guest LBR support on KVM

2021-03-25 Thread Like Xu
Starting from v5.12, KVM reports guest LBR and extra_regs support when the host has relevant support. Just delete this part of the comment and fix a typo incidentally. Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/core.c | 3 +-- 1 file

Re: [PATCH v4 RESEND 3/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-23 Thread Like Xu
On 2021/3/24 12:04, Namhyung Kim wrote: On Wed, Mar 24, 2021 at 12:47 PM Like Xu wrote: Hi Namhyung, On 2021/3/24 9:32, Namhyung Kim wrote: Hello, On Mon, Mar 22, 2021 at 3:14 PM Like Xu wrote: +void reserve_lbr_buffers(struct perf_event *event) +{ + struct kmem_cache *kmem_cache

Re: [PATCH v4 RESEND 3/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-23 Thread Like Xu
Hi Namhyung, On 2021/3/24 9:32, Namhyung Kim wrote: Hello, On Mon, Mar 22, 2021 at 3:14 PM Like Xu wrote: +void reserve_lbr_buffers(struct perf_event *event) +{ + struct kmem_cache *kmem_cache = x86_get_pmu()->task_ctx_cache; + struct cpu_hw_events *cpuc; + int

Re: [PATCH v4 RESEND 4/5] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR

2021-03-23 Thread Like Xu
On 2021/3/24 5:49, Peter Zijlstra wrote: On Mon, Mar 22, 2021 at 02:06:34PM +0800, Like Xu wrote: The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will generate #GP for this MSR access, thereby preventing the initialization of the guest LBR. Fixes: 47125db27e47 ("perf/x86/

Re: [PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-03-23 Thread Like Xu
On 2021/3/24 5:38, Peter Zijlstra wrote: On Mon, Mar 22, 2021 at 02:06:32PM +0800, Like Xu wrote: If the platform supports LBR_INFO register, the x86_pmu.lbr_info will be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO You mean: intel_pmu_lbr_*init*(). '?&#x

[PATCH v4 RESEND 5/5] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h

2021-03-21 Thread Like Xu
The ARCH_LBR_CTL_MASK will be reused for Arch LBR emulation in the KVM. Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 2 -- arch/x86/include/asm/msr-index.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel

[PATCH v4 RESEND 0/5] x86: The perf/x86 changes to support guest Arch LBR

2021-03-21 Thread Like Xu
more details in each commit and feel free to comment. Like Xu (5): perf/x86/intel: Fix the comment about guest LBR support on KVM perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region perf/x86/lbr: S

[PATCH v4 RESEND 1/5] perf/x86/intel: Fix the comment about guest LBR support on KVM

2021-03-21 Thread Like Xu
Starting from v5.12, KVM reports guest LBR and extra_regs support when the host has relevant support. Just delete this part of the comment and fix a typo incidentally. Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/core.c | 3 +-- 1 file

[PATCH v4 RESEND 4/5] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR

2021-03-21 Thread Like Xu
The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will generate #GP for this MSR access, thereby preventing the initialization of the guest LBR. Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR") Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewe

[PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-03-21 Thread Like Xu
_x to hold metadata for the operation, including mispredict, TSX, and elapsed cycle time information. Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lb

[PATCH v4 RESEND 3/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-21 Thread Like Xu
uggested-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/core.c | 8 +--- arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/lbr.c | 22 -- arch/x86/events/perf_event.h | 8 +++- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a

[PATCH v2] x86: Update guest LBR tests for Architectural LBR

2021-03-14 Thread Like Xu
will record a running trace of the most recent branches guest taken in the LBR entries for guest to read. Signed-off-by: Like Xu --- x86/pmu_lbr.c | 88 +-- 1 file changed, 79 insertions(+), 9 deletions(-) diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c

[PATCH v4 10/11] KVM: x86: Refine the matching and clearing logic for supported_xss

2021-03-14 Thread Like Xu
Refine the code path of the existing clearing of supported_xss in this way: initialize the supported_xss with the filter of KVM_SUPPORTED_XSS mask and update its value in a bit clear manner (rather than bit setting). Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/vmx

[PATCH v4 11/11] KVM: x86: Add XSAVE Support for Architectural LBRs

2021-03-14 Thread Like Xu
leakage of host records via XSAVES. In this case, the guest results may be inaccurate as the legacy LBR. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ arch/x86/kvm/vmx/vmx.c | 4 +++- arch/x86/kvm/x86.c | 2 +- 3 files changed, 6 insertions(+), 2 deletions

[PATCH v4 09/11] KVM: x86: Expose Architectural LBR CPUID leaf

2021-03-14 Thread Like Xu
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities. Currently, KVM only supports the current host LBR depth for guests, which is also the maximum supported depth on the host. Signed-off-by: Like Xu

[PATCH v4 08/11] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field

2021-03-14 Thread Like Xu
KVM will bypass the host/guest x86 cpu model check and the records msrs can still be pass-through to guest as usual and work like a model-specific LBR. KVM is consistent with the host and does not support the LER entry. Signed-off-by: Like Xu --- arch/x86/include/asm/vmx.h | 2

[PATCH v4 06/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR

2021-03-14 Thread Like Xu
en the Arch LBR records MSRs are pass-through to the guest. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 43 arch/x86/kvm/vmx/vmx.h | 3 +++ 2 files changed, 46 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kv

[PATCH v4 03/11] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR

2021-03-14 Thread Like Xu
tural LBR") Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7bb96ac87615..0338e354826d 100644 ---

[PATCH v4 05/11] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h

2021-03-14 Thread Like Xu
The ARCH_LBR_CTL_MASK will be reused for LBR emulation in the KVM. Cc: Kan Liang Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Ingo Molnar Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 2 -- arch/x86/include/asm/msr-index.h | 1 + 2 files changed, 1 insertion(+), 2 deletions

[PATCH v4 07/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR

2021-03-14 Thread Like Xu
t Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no meaning. It can be written to 0 or 1, but reads will always return 0. Like IA32_DEBUGCTL, IA32_ARCH_LBR_CTL msr is also reserved on INIT. Signed-off-by: Like Xu --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx/pmu_in

[PATCH v4 04/11] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-14 Thread Like Xu
774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read") Suggested-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/core.c | 8 +--- arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/lbr.c | 22 -- arch/x86/events/perf_event.h | 8

[PATCH v4 02/11] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-03-14 Thread Like Xu
_x to hold metadata for the operation, including mispredict, TSX, and elapsed cycle time information. Cc: Kan Liang Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Ingo Molnar Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/lbr.c | 4 +--- 1 file chang

[PATCH v4 01/11] perf/x86/intel: Fix the comment about guest LBR support on KVM

2021-03-14 Thread Like Xu
Starting from v5.12, KVM reports guest LBR and extra_regs support when the host has relevant support. Just delete this part of the comment and fix a typo. Cc: Kan Liang Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Ingo Molnar Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi

[PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling

2021-03-14 Thread Like Xu
t;host_lbrctlmsr to save/restore host values; - Add KVM_SUPPORTED_XSS to refactoring supported_xss; - Clear Arch_LBR ans its XSS bit if it's not supported; - Add negative testing to the related kvm-unit-tests; - Refine code and commit messages; Previous: https://lore.kernel.org/kvm/20210303135756.

Re: [PATCH] x86/perf: Fix guest_get_msrs static call if there is no PMU

2021-03-08 Thread Like Xu
te nop. Ultimately, this causes VMX abort on VM-Exit due to KVM putting random garbage from the stack into the MSR load list. Fixes: abd562df94d1 ("x86/perf: Use static_call for x86_pmu.guest_get_msrs") Cc: Like Xu Cc: Paolo Bonzini Cc: Jim Mattson Cc: k...@vger.kernel.o

Re: [PATCH v3 9/9] KVM: x86: Add XSAVE Support for Architectural LBRs

2021-03-03 Thread Like Xu
On 2021/3/4 2:03, Sean Christopherson wrote: On Wed, Mar 03, 2021, Like Xu wrote: diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 034708a3df20..ec4593e0ee6d 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7268,6 +7268,8 @@ static __init void

[PATCH v3 8/9] KVM: x86: Expose Architectural LBR CPUID leaf

2021-03-03 Thread Like Xu
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities. Currently, KVM only supports the current host LBR depth for guests, which is also the maximum supported depth on the host. Signed-off-by: Like Xu

[kvm-unit-tests PATCH] x86: Update guest LBR tests for Architectural LBR

2021-03-03 Thread Like Xu
guest taken in the LBR entries for guest to read. Signed-off-by: Like Xu --- x86/pmu_lbr.c | 62 ++- 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c index 3bd9e9f..588aec8 100644 --- a/x86/pmu_lbr.c +++

[PATCH v3 9/9] KVM: x86: Add XSAVE Support for Architectural LBRs

2021-03-03 Thread Like Xu
leakage of host records via XSAVES. In this case, the guest results may be inaccurate as the legacy LBR. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ arch/x86/kvm/vmx/vmx.c | 2 ++ arch/x86/kvm/x86.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch

[PATCH v3 4/9] perf/x86/lbr: Use GFP_ATOMIC for cpuc->lbr_xsave memory allocation

2021-03-03 Thread Like Xu
x50 [ 54.317698] do_syscall_64+0x33/0x40 [ 54.318390] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Fix it by allocating this part of memory with GFP_ATOMIC mask. Cc: Peter Zijlstra Fixes: c085fb8774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read") Suggested-by: Kan Liang Signed

[PATCH v3 6/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR

2021-03-03 Thread Like Xu
t Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no meaning. It can be written to 0 or 1, but reads will always return 0. On the vmx_vcpu_reset(), the IA32_LBR_CTL will be cleared to 0. Signed-off-by: Like Xu --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx/pmu_intel.c | 27 ++-

[PATCH v3 7/9] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field

2021-03-03 Thread Like Xu
usual and work like a model-specific LBR. KVM is consistent with the host and does not support the LER entry. Signed-off-by: Like Xu --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx/capabilities.h | 25 + arch/x86/kvm/vmx/pmu_intel.c| 27 +++

[PATCH v3 5/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR

2021-03-03 Thread Like Xu
en the Arch LBR records MSRs are pass-through to the guest. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 43 arch/x86/kvm/vmx/vmx.h | 3 +++ 2 files changed, 46 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kv

[PATCH v3 3/9] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR

2021-03-03 Thread Like Xu
The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will generate #GP for this MSR access, thereby preventing the initialization of the guest LBR. Cc: Peter Zijlstra Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR") Signed-off-by: Like Xu Reviewed-by:

[PATCH v3 0/9] KVM: x86/pmu: Guest Architectural LBR Enabling

2021-03-03 Thread Like Xu
pu_reset(); - Refine intel_pmu_lbr_is_compatible(); - Simplify lbr_enable check and its usage; - Add Arch LBR msrs to is_valid_passthrough_msr(); - Make XSAVE support for Arch LBR as a separate patch; Previous: https://lore.kernel.org/kvm/20210203135714.318356-1-like...@linux.intel.com/ Like Xu

[PATCH v3 2/9] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-03-03 Thread Like Xu
_x to hold metadata for the operation, including mispredict, TSX, and elapsed cycle time information. Cc: Peter Zijlstra Reviewed-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b

[PATCH v3 1/9] perf/x86/intel: Fix a comment about guest LBR support

2021-03-03 Thread Like Xu
Starting from v5.12, KVM reports guest LBR and extra_regs support when the host has relevant support. Cc: Peter Zijlstra Reviewed-by: Kan Liang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel

Re: [PATCH v2 1/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR

2021-03-01 Thread Like Xu
On 2021/3/2 6:34, Sean Christopherson wrote: On Wed, Feb 03, 2021, Like Xu wrote: @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, return true; } +/* + * Check if the requested depth values is supported + * based on the bits [0:7] of the

[PATCH 2/2] KVM: vmx/pmu: Clear DEBUGCTLMSR_LBR bit on the debug breakpoint event

2021-02-22 Thread Like Xu
When the processor that support model-specific LBR generates a debug breakpoint event, it automatically clears the LBR flag. This action does not clear previously stored LBR stack MSRs. (Intel SDM 17.4.2) Signed-off-by: Like Xu --- arch/x86/kvm/vmx/vmx.c | 5 + 1 file changed, 5 insertions

[PATCH 1/2] KVM: vmx/pmu: Fix dummy check if lbr_desc->event is created

2021-02-22 Thread Like Xu
If lbr_desc->event is successfully created, the intel_pmu_create_ guest_lbr_event() will return 0, otherwise it will return -ENOENT, and then jump to LBR msrs dummy handling. Fixes: 1b5ac3226a1a ("KVM: vmx/pmu: Pass-through LBR msrs when the guest LBR event is ACTIVE") Signed-of

Re: [PATCH] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-02-17 Thread Like Xu
Hi Peter, Would you help pick up this patch so that we can enable guest Arch LBR? --- thx,likexu On 2021/2/3 15:03, Like Xu wrote: If the platform supports LBR_INFO register, the x86_pmu.lbr_info will be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO i

[PATCH v2 4/4] KVM: x86: Expose Architectural LBR CPUID and its XSAVES bit

2021-02-03 Thread Like Xu
purposes once IA32_XSS [bit 15] is set. XSAVE support for Arch LBRs is enumerated in CPUID.(EAX=0DH, ECX=0FH). Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.c | 23 +++ arch/x86/kvm/vmx/vmx.c | 2 ++ arch/x86/kvm/x86.c | 10 +- 3 files changed, 34 insertions(+), 1

[PATCH v2 3/4] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field

2021-02-03 Thread Like Xu
X86_FEATURE_ARCH_LBR to enable guest LBR, which is equivalent to the legacy LBR_FMT setting. The Arch LBR feature could bypass the host/guest x86_model check and the records msrs can still be pass-through to guest as usual and work like the legacy LBR. Signed-off-by: Like Xu --- arch/x86/include/

[PATCH v2 1/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR

2021-02-03 Thread Like Xu
a software write to MSR_ARCH_LBR_DEPTH, all LBR entries are reset to 0. Emulate the reset behavior by introducing lbr_desc->arch_lbr_reset and sync it to the host MSR_ARCH_LBR_DEPTH msr when the guest LBR event is ACTIVE and the LBR records msrs are pass-through to the guest. Signed-off-by: L

[PATCH v2 2/4] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR

2021-02-03 Thread Like Xu
LBR usage and the guest value of MSR_ARCH_LBR_CTL is written to this field on all VM exits. Signed-off-by: Like Xu --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx/pmu_intel.c | 14 ++ arch/x86/kvm/vmx/vmx.c | 7 +++ 3 files changed, 23 insertions(+) diff --git

[PATCH v2 0/4] KVM: x86/pmu: Guest Architectural LBR Enabling

2021-02-03 Thread Like Xu
age; Previous: https://lore.kernel.org/kvm/20200731074402.8879-1-like...@linux.intel.com/ Like Xu (4): KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field KVM: x86: Exp

[PATCH] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

2021-02-02 Thread Like Xu
_x to hold metadata for the operation, including mispredict, TSX, and elapsed cycle time information. Cc: Kan Liang Cc: Peter Zijlstra (Intel) Signed-off-by: Like Xu --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b

[PATCH] KVM: vmx/pmu: Add VMCS fields check before exposing LBR_FMT

2021-02-02 Thread Like Xu
Before KVM exposes guest LBR_FMT perf capabilities, it needs to check whether VMCS has GUEST_IA32_DEBUGCTL guest status field and vmx switch support on IA32_DEBUGCTL MSR (including VM_EXIT_SAVE_DEBUG_CONTROLS and VM_ENTRY_LOAD_DEBUG_CONTROLS). It helps nested LBR enablement. Signed-off-by: Like

[PATCH v14 07/11] KVM: vmx/pmu: Reduce the overhead of LBR pass-through or cancellation

2021-01-31 Thread Like Xu
When the LBR records msrs has already been pass-through, there is no need to call vmx_update_intercept_for_lbr_msrs() again and again, and vice versa. Signed-off-by: Like Xu Reviewed-by: Andi Kleen --- arch/x86/kvm/vmx/pmu_intel.c | 13 + arch/x86/kvm/vmx/vmx.h | 3 +++ 2

[PATCH v14 11/11] selftests: kvm/x86: add test for pmu msr MSR_IA32_PERF_CAPABILITIES

2021-01-31 Thread Like Xu
This test will check the effect of various CPUID settings on the MSR_IA32_PERF_CAPABILITIES MSR, check that whatever user space writes with KVM_SET_MSR is _not_ modified from the guest and can be retrieved with KVM_GET_MSR, and check that invalid LBR formats are rejected. Signed-off-by: Like Xu

[PATCH v14 10/11] KVM: vmx/pmu: Expose LBR_FMT in the MSR_IA32_PERF_CAPABILITIES

2021-01-31 Thread Like Xu
()) and the vcpu model is compatible with the host one. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 57b940c613ab..c49f3ee8eca8 100644

[PATCH v14 08/11] KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI

2021-01-31 Thread Like Xu
lso, guest needs to re-enable IA32_DEBUGCTL.LBR to resume recording branches. Signed-off-by: Like Xu Reviewed-by: Andi Kleen --- arch/x86/kvm/pmu.c | 5 - arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/capabilities.h | 4 +++- arch/x86/kvm/vmx/pmu_intel

[PATCH v14 10/11] KVM: vmx/pmu: Expose LBR_FMT in the MSR_IA32_PERF_CAPABILITIES

2021-01-31 Thread Like Xu
()) and the vcpu model is compatible with the host one. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 57b940c613ab..c49f3ee8eca8 100644

[PATCH v14 09/11] KVM: vmx/pmu: Release guest LBR event via lazy release mechanism

2021-01-31 Thread Like Xu
LBR event as a bland event of a vPMC counter and release it as usual. Also, the pass-through state of LBR records msrs is cancelled. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 3 +++ arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 21 - 3

[PATCH v14 11/11] selftests: kvm/x86: add test for pmu msr MSR_IA32_PERF_CAPABILITIES

2021-01-31 Thread Like Xu
This test will check the effect of various CPUID settings on the MSR_IA32_PERF_CAPABILITIES MSR, check that whatever user space writes with KVM_SET_MSR is _not_ modified from the guest and can be retrieved with KVM_GET_MSR, and check that invalid LBR formats are rejected. Signed-off-by: Like Xu

[PATCH v14 08/11] KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI

2021-01-31 Thread Like Xu
lso, guest needs to re-enable IA32_DEBUGCTL.LBR to resume recording branches. Signed-off-by: Like Xu Reviewed-by: Andi Kleen --- arch/x86/kvm/pmu.c | 5 - arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/capabilities.h | 4 +++- arch/x86/kvm/vmx/pmu_intel

[PATCH v14 07/11] KVM: vmx/pmu: Reduce the overhead of LBR pass-through or cancellation

2021-01-31 Thread Like Xu
When the LBR records msrs has already been pass-through, there is no need to call vmx_update_intercept_for_lbr_msrs() again and again, and vice versa. Signed-off-by: Like Xu Reviewed-by: Andi Kleen --- arch/x86/kvm/vmx/pmu_intel.c | 13 + arch/x86/kvm/vmx/vmx.h | 3 +++ 2

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