Re: [PATCH] drm/bridge: adv7511: Attach to DSI host at probe time

MIPI DSI host registers it's bridge such that it is > available for the upstream device to connect to. > > Signed-off-by: Matt Redfearn > > --- > > drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 9 + > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --g

[PATCH v3 2/2] MIPS: memset.S: Add comments to fault fixup handlers

It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to assist those who follow. Signed-off-by: Matt Redfearn <matt.redfe...@mips.

[PATCH v3 2/2] MIPS: memset.S: Add comments to fault fixup handlers

It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to assist those who follow. Signed-off-by: Matt Redfearn --- Changes in v3

[PATCH v3 1/2] MIPS: memset.S: Fix byte_fixup for MIPSr6

Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support") Cc: sta...@vger.kernel.org Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: New patch to fix fault handling during MIPSr6 version of setting unaligned bytes. Changes in v2: None arch/mips/

[PATCH v3 1/2] MIPS: memset.S: Fix byte_fixup for MIPSr6

Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support") Cc: sta...@vger.kernel.org Signed-off-by: Matt Redfearn --- Changes in v3: New patch to fix fault handling during MIPSr6 version of setting unaligned bytes. Changes in v2: None arch/mips/lib/memset.S | 3 ++- 1 file chan

Re: [PATCH v2 4/4] MIPS: memset.S: Add comments to fault fixup handlers

Hi James, On 21/05/18 17:14, James Hogan wrote: On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote: diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 1cc306520a55..a06dabe99d4b 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -231,16 +231,25

Re: [PATCH v2 4/4] MIPS: memset.S: Add comments to fault fixup handlers

Hi James, On 21/05/18 17:14, James Hogan wrote: On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote: diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 1cc306520a55..a06dabe99d4b 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -231,16 +231,25

Re: [PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand

Hi James, On 16/05/18 19:05, James Hogan wrote: On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote: Previously when performance counters are per-core, rather than per-thread, the number available were divided by 2 on detection, and the counters used by each thread in a core were

Re: [PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand

Hi James, On 16/05/18 19:05, James Hogan wrote: On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote: Previously when performance counters are per-core, rather than per-thread, the number available were divided by 2 on detection, and the counters used by each thread in a core were

Re: [PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads

Hi James, On 16/05/18 18:59, James Hogan wrote: On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote: diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 7e2b7d38a774..fe50986e83c6 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch

Re: [PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads

Hi James, On 16/05/18 18:59, James Hogan wrote: On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote: diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 7e2b7d38a774..fe50986e83c6 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch

[PATCH v4] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> Tested-by

[PATCH v4] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn Tested-by: Florian Fainelli --- Chan

Re: [PATCH v2] clocksource/drivers/mips-gic-timer: Add pr_fmt and reword pr_* messages

On 29/03/18 10:49, Matt Redfearn wrote: Several messages from the MIPS GIC driver include the text "GIC", "GIC timer", etc, but the format is not standard. Add a pr_fmt of "mips-gic-timer: " and reword the messages now that they will be prefixed with the dri

Re: [PATCH v2] clocksource/drivers/mips-gic-timer: Add pr_fmt and reword pr_* messages

On 29/03/18 10:49, Matt Redfearn wrote: Several messages from the MIPS GIC driver include the text "GIC", "GIC timer", etc, but the format is not standard. Add a pr_fmt of "mips-gic-timer: " and reword the messages now that they will be prefixed with the dri

Re: [PATCH 4.17 2/2] ssb: make SSB_PCICORE_HOSTMODE depend on SSB = y

Hi, On 10/05/18 12:26, Michael Büsch wrote: On Thu, 10 May 2018 13:20:01 +0200 Rafał Miłecki wrote: On 10 May 2018 at 13:17, Michael Büsch wrote: On Thu, 10 May 2018 13:14:01 +0200 Rafał Miłecki wrote: From: Rafał Miłecki

Re: [PATCH 4.17 2/2] ssb: make SSB_PCICORE_HOSTMODE depend on SSB = y

Hi, On 10/05/18 12:26, Michael Büsch wrote: On Thu, 10 May 2018 13:20:01 +0200 Rafał Miłecki wrote: On 10 May 2018 at 13:17, Michael Büsch wrote: On Thu, 10 May 2018 13:14:01 +0200 Rafał Miłecki wrote: From: Rafał Miłecki SSB_PCICORE_HOSTMODE protects MIPS specific code that calls

Re: Regression caused by commit 882164a4a928

Hi Rafał, On 10/05/18 11:41, Rafał Miłecki wrote: On 7 May 2018 at 17:44, Larry Finger wrote: Although commit 882164a4a928 ("ssb: Prevent build of PCI host features in module") appeared to be harmless, it leads to complete failure of drivers b43. and b43legacy, and

Re: Regression caused by commit 882164a4a928

Hi Rafał, On 10/05/18 11:41, Rafał Miłecki wrote: On 7 May 2018 at 17:44, Larry Finger wrote: Although commit 882164a4a928 ("ssb: Prevent build of PCI host features in module") appeared to be harmless, it leads to complete failure of drivers b43. and b43legacy, and likely affects b44 as well.

Re: Regression caused by commit 882164a4a928

Hi Michael, On 09/05/18 17:27, Michael Büsch wrote: On Wed, 9 May 2018 13:55:43 +0100 Matt Redfearn <matt.redfe...@mips.com> wrote: Hi Larry On 07/05/18 16:44, Larry Finger wrote: Matt, Although commit 882164a4a928 ("ssb: Prevent build of PCI host features in module

Re: Regression caused by commit 882164a4a928

Hi Michael, On 09/05/18 17:27, Michael Büsch wrote: On Wed, 9 May 2018 13:55:43 +0100 Matt Redfearn wrote: Hi Larry On 07/05/18 16:44, Larry Finger wrote: Matt, Although commit 882164a4a928 ("ssb: Prevent build of PCI host features in module") appeared to be harmless, it leads t

Re: [REVIEW][PATCH 08/22] signal/mips: Use force_sig_fault where appropriate

Hi Eric, On 10/05/18 03:39, Eric W. Biederman wrote: Matt Redfearn <matt.redfe...@mips.com> writes: Hi Eric, On 20/04/18 15:37, Eric W. Biederman wrote: Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong

Re: [REVIEW][PATCH 08/22] signal/mips: Use force_sig_fault where appropriate

Hi Eric, On 10/05/18 03:39, Eric W. Biederman wrote: Matt Redfearn writes: Hi Eric, On 20/04/18 15:37, Eric W. Biederman wrote: Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out

Re: [REVIEW][PATCH 08/22] signal/mips: Use force_sig_fault where appropriate

Hi Eric, On 20/04/18 15:37, Eric W. Biederman wrote: Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper

Re: [REVIEW][PATCH 08/22] signal/mips: Use force_sig_fault where appropriate

Hi Eric, On 20/04/18 15:37, Eric W. Biederman wrote: Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper

Re: Regression caused by commit 882164a4a928

. I've tested the above patch and it does work for MIPS (preventing the PCICORE being built into the module). Tested-by: Matt Redfearn <matt.redfe...@mips.com> Thanks & sorry again for the breakage, Matt Thanks, Larry

Re: Regression caused by commit 882164a4a928

. I've tested the above patch and it does work for MIPS (preventing the PCICORE being built into the module). Tested-by: Matt Redfearn Thanks & sorry again for the breakage, Matt Thanks, Larry

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 13:27, Robert Richter wrote: On 04.05.18 12:03:12, Matt Redfearn wrote: As said, oprofile version 0.9.x is still available for cpus that do not support perf. What is the breakage? The breakage I originally set out to fix was the MT support in perf. https://www.linux

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 13:27, Robert Richter wrote: On 04.05.18 12:03:12, Matt Redfearn wrote: As said, oprofile version 0.9.x is still available for cpus that do not support perf. What is the breakage? The breakage I originally set out to fix was the MT support in perf. https://www.linux

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 11:26, Robert Richter wrote: On 04.05.18 10:54:32, Matt Redfearn wrote: perf is available for MIPS and supports many more CPU types than oprofile. oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile support from the MIPS kernel would not break

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 11:26, Robert Richter wrote: On 04.05.18 10:54:32, Matt Redfearn wrote: perf is available for MIPS and supports many more CPU types than oprofile. oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile support from the MIPS kernel would not break

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 10:30, Robert Richter wrote: On 24.04.18 14:15:58, Matt Redfearn wrote: On 24/04/18 14:05, James Hogan wrote: On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: Since it appears that MIPS oprofile support is currently broken, core oprofile is not getting

Re: [RFC PATCH] MIPS: Oprofile: Drop support

Hi Robert, On 04/05/18 10:30, Robert Richter wrote: On 24.04.18 14:15:58, Matt Redfearn wrote: On 24/04/18 14:05, James Hogan wrote: On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: Since it appears that MIPS oprofile support is currently broken, core oprofile is not getting

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 24/04/18 14:05, James Hogan wrote: On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: Since it appears that MIPS oprofile support is currently broken, core oprofile is not getting many updates and not as many architectures implement support for it compared to perf, remove

Re: [RFC PATCH] MIPS: Oprofile: Drop support

On 24/04/18 14:05, James Hogan wrote: On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: Since it appears that MIPS oprofile support is currently broken, core oprofile is not getting many updates and not as many architectures implement support for it compared to perf, remove

[RFC PATCH] MIPS: Oprofile: Drop support

2878] [<805b24dc>] do_execve+0x38/0x44 [ 97.297669] [<80415a58>] syscall_common+0x34/0x58 [ 97.302924] Code: afb0003c 8e22d4e0 afa20034 <8c820008> 14400170 24030020 8f82000c 26460010 00a09825 Since it appears that MIPS oprofile support is currently broken, core oprofile i

[RFC PATCH] MIPS: Oprofile: Drop support

2878] [<805b24dc>] do_execve+0x38/0x44 [ 97.297669] [<80415a58>] syscall_common+0x34/0x58 [ 97.302924] Code: afb0003c 8e22d4e0 afa20034 <8c820008> 14400170 24030020 8f82000c 26460010 00a09825 Since it appears that MIPS oprofile support is currently broken, core oprofile

[PATCH] cifs: smbd: Fix printk format warning for iov on the stack

3: warning: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' [-Wformat=] Change the format specifier to %zu for the size_t argument. Fixes: 4863cc758216 ("cifs: smbd: Avoid allocating iov on the stack") Signed-off-by: Matt Redfearn <

[PATCH] cifs: smbd: Fix printk format warning for iov on the stack

3: warning: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' [-Wformat=] Change the format specifier to %zu for the size_t argument. Fixes: 4863cc758216 ("cifs: smbd: Avoid allocating iov on the stack") Signed-off-by: Matt Redfearn ---

Re: [PATCH v3 0/7] MIPS: perf: MT fixes and improvements

On 20/04/18 23:51, Florian Fainelli wrote: On 04/20/2018 03:23 AM, Matt Redfearn wrote: This series addresses a few issues with how the MIPS performance counters code supports the hardware multithreading MT ASE. Firstly, implementations of the MT ASE may implement performance counters per

Re: [PATCH v3 0/7] MIPS: perf: MT fixes and improvements

On 20/04/18 23:51, Florian Fainelli wrote: On 04/20/2018 03:23 AM, Matt Redfearn wrote: This series addresses a few issues with how the MIPS performance counters code supports the hardware multithreading MT ASE. Firstly, implementations of the MT ASE may implement performance counters per

Re: [PATCH] serial: 8250_early: Setup divider when uartclk is passed

Hi Michal On 23/04/18 10:18, Michal Simek wrote: device->baud is always non zero value because it is checked already in early_serial8250_setup() before init_port is called. True, currently init_port is only called from the one location and so the test is a little redundant, though I don't

Re: [PATCH] serial: 8250_early: Setup divider when uartclk is passed

Hi Michal On 23/04/18 10:18, Michal Simek wrote: device->baud is always non zero value because it is checked already in early_serial8250_setup() before init_port is called. True, currently init_port is only called from the one location and so the test is a little redundant, though I don't

Re: [RFC. PATCH] earlycon: Remove hardcoded port->uartclk initialization in of_setup_earlycon

a MIPS pistachio board. As long as the bootloader has configured the uart divisor, earlycon should work as long as my patch "serial: 8250_early: Only set divisor if valid clk & baud" is applied to avoid a bad divisor getting calculated. Tested-by: Matt Redfearn <matt.redfe...@

Re: [RFC. PATCH] earlycon: Remove hardcoded port->uartclk initialization in of_setup_earlycon

as the bootloader has configured the uart divisor, earlycon should work as long as my patch "serial: 8250_early: Only set divisor if valid clk & baud" is applied to avoid a bad divisor getting calculated. Tested-by: Matt Redfearn Thanks, Matt --- drivers/tty/serial/earlycon.c

Re: [PATCH 3.18 45/52] MIPS: memset.S: Fix clobber of v1 in last_fixup

let me know. -- From: Matt Redfearn <matt.redfe...@mips.com> commit c96eebf07692e53bf4dd5987510d8b550e793598 upstream. The label .Llast_fixup\@ is jumped to on page fault within the final byte set loop of memset (on < MIPSR6 architectures). For some reason, in this fault

Re: [PATCH 3.18 45/52] MIPS: memset.S: Fix clobber of v1 in last_fixup

. -- From: Matt Redfearn commit c96eebf07692e53bf4dd5987510d8b550e793598 upstream. The label .Llast_fixup\@ is jumped to on page fault within the final byte set loop of memset (on < MIPSR6 architectures). For some reason, in this fault handler, the v1 register is randomly set to a2 & S

[PATCH v3 2/7] MIPS: perf: More robustly probe for the presence of per-tc counters

-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: Use flag in cpu_data set by cpu_probe.c to indicate feature presence. Changes in v2: None arch/mips/include/asm/cpu-features.h | 7 +++ arch/mips/kernel/perf_event_mipsxx.c | 3 --- arch/mips/oprofile/op_model_mipsxx.c | 2

[PATCH v3 2/7] MIPS: perf: More robustly probe for the presence of per-tc counters

-by: Matt Redfearn --- Changes in v3: Use flag in cpu_data set by cpu_probe.c to indicate feature presence. Changes in v2: None arch/mips/include/asm/cpu-features.h | 7 +++ arch/mips/kernel/perf_event_mipsxx.c | 3 --- arch/mips/oprofile/op_model_mipsxx.c | 2 -- 3 files changed, 7

[PATCH v3 7/7] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Chan

[PATCH v3 7/7] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn --- Changes in v3: None Changes in

[PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand

0.005179533 seconds time elapsed Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u 0.005179467 seconds time elapsed Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: - rebase on ne

[PATCH v3 6/7] MIPS: perf: Fold vpe_id() macro into it's one last usage

set the counter to count the relevant VPE. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: None Changes in v2: Since BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. arch/mips/kernel/perf_event_mipsxx.

[PATCH v3 6/7] MIPS: perf: Fold vpe_id() macro into it's one last usage

set the counter to count the relevant VPE. Signed-off-by: Matt Redfearn --- Changes in v3: None Changes in v2: Since BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. arch/mips/kernel/perf_event_mipsxx.c | 18 -- 1 file

[PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand

0.005179533 seconds time elapsed Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u 0.005179467 seconds time elapsed Signed-off-by: Matt Redfearn --- Changes in v3: - rebase on new feature detection

[PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads

t -e instructions:u,branches:u ./test_prog Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: None Changes in v2: Fix mipsxx_pmu_enable_event for !

[PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads

t -e instructions:u,branches:u ./test_prog Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u Signed-off-by: Matt Redfearn --- Changes in v3: None Changes in v2: Fix mipsxx_pmu_enable_event for !#ifdef CONFIG_MIPS_MT_SMP

[PATCH v3 3/7] MIPS: perf: Use correct VPE ID when setting up VPE tracing

Fix this by replacing smp_processor_id() with cpu_vpe_id(_cpu_data), in the vpe_id() macro, and pass vpe_id() to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also be removed since they no longer apply. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: Non

[PATCH v3 3/7] MIPS: perf: Use correct VPE ID when setting up VPE tracing

Fix this by replacing smp_processor_id() with cpu_vpe_id(_cpu_data), in the vpe_id() macro, and pass vpe_id() to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also be removed since they no longer apply. Signed-off-by: Matt Redfearn --- Changes in v3: None Changes in v2: None arch/m

[PATCH v3 1/7] MIPS: Probe for MIPS MT perf counters per TC

CPUs known to implement this bit and the MT ASE, specifically, the 34K, 1004K and interAptiv. Once the presence of the per-tc counter is indicated in cpu_data, tests for it can be updated to use this flag. Suggested-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <m

[PATCH v3 1/7] MIPS: Probe for MIPS MT perf counters per TC

CPUs known to implement this bit and the MT ASE, specifically, the 34K, 1004K and interAptiv. Once the presence of the per-tc counter is indicated in cpu_data, tests for it can be updated to use this flag. Suggested-by: James Hogan Signed-off-by: Matt Redfearn --- Changes in v3: New patch

[PATCH v3 0/7] MIPS: perf: MT fixes and improvements

BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. New patch to fix BMIPS5000 system mode perf. Matt Redfearn (7): MIPS: Probe for MIPS MT perf counters per TC MIPS: perf: More robustly probe for the presence of per-tc counters MIPS: perf

[PATCH v3 0/7] MIPS: perf: MT fixes and improvements

BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. New patch to fix BMIPS5000 system mode perf. Matt Redfearn (7): MIPS: Probe for MIPS MT perf counters per TC MIPS: perf: More robustly probe for the presence of per-tc counters MIPS: perf

Re: [PATCH v6 3/4] MIPS: vmlinuz: Use generic ashldi3

Hi James, On 18/04/18 00:09, James Hogan wrote: On Wed, Apr 11, 2018 at 08:50:18AM +0100, Matt Redfearn wrote: diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index adce180f3ee4..e03f522c33ac 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips

Re: [PATCH v6 3/4] MIPS: vmlinuz: Use generic ashldi3

Hi James, On 18/04/18 00:09, James Hogan wrote: On Wed, Apr 11, 2018 at 08:50:18AM +0100, Matt Redfearn wrote: diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index adce180f3ee4..e03f522c33ac 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips

[PATCH v2 4/4] MIPS: memset.S: Add comments to fault fixup handlers

It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to addist those who follow. Signed-off-by: Matt Redfearn <matt.redfe...@mips.

[PATCH v2 4/4] MIPS: memset.S: Add comments to fault fixup handlers

It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to addist those who follow. Signed-off-by: Matt Redfearn --- Changes in v2: - Add

[PATCH v2 3/4] MIPS: memset.S: Reinstate delay slot indentation

convention for all instructions in a branch delay slot. This effectively reverts the above commit, plus other locations introduced with MIPSR6 support. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: - Rebase delay slot indentation on v3 of "MIPS: memset.S: Fix ret

[PATCH v2 3/4] MIPS: memset.S: Reinstate delay slot indentation

convention for all instructions in a branch delay slot. This effectively reverts the above commit, plus other locations introduced with MIPSR6 support. Signed-off-by: Matt Redfearn --- Changes in v2: - Rebase delay slot indentation on v3 of "MIPS: memset.S: Fix return of __clear_user from Lpartia

[PATCH v2 2/4] MIPS: uaccess: Add micromips clobbers to bzero invocation

er.kernel.org Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: None arch/mips/include/asm/uaccess.h | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index b713069

[PATCH v2 2/4] MIPS: uaccess: Add micromips clobbers to bzero invocation

The micromips implementation of bzero additionally clobbers registers t7 & t8. Specify this in the clobbers list when invoking bzero. Reported-by: James Hogan Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library function.") Cc: sta...@vger.kernel.org Signe

[PATCH v2 1/4] MIPS: memset.S: Fix clobber of v1 in last_fixup

ould not be set is already contained in a2, the andi placing a value in v1 is not necessary and actively harmful in clobbering v1. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Reported-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <matt.redf

[PATCH v2 1/4] MIPS: memset.S: Fix clobber of v1 in last_fixup

ould not be set is already contained in a2, the andi placing a value in v1 is not necessary and actively harmful in clobbering v1. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Reported-by: James Hogan Signed-off-by: Matt Redfearn --- Changes in v2: None arc

[PATCH v3] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

6.12-rc2") Cc: sta...@vger.kernel.org Suggested-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v3: - Just fix the issue at hand Changes in v2: - Use James Hogan's suggestion of replacing t1 with a0 to get the correct remain

[PATCH v3] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

6.12-rc2") Cc: sta...@vger.kernel.org Suggested-by: James Hogan Signed-off-by: Matt Redfearn --- Changes in v3: - Just fix the issue at hand Changes in v2: - Use James Hogan's suggestion of replacing t1 with a0 to get the correct remainder count. arch/mips/lib/memset.S | 2 +- 1 file cha

[PATCH 2/3] MIPS: uaccess: Add micromips clobbers to bzero invocation

er.kernel.org Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/include/asm/uaccess.h | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index b71306947290..06629011a434 100644 -

[PATCH 2/3] MIPS: uaccess: Add micromips clobbers to bzero invocation

The micromips implementation of bzero additionally clobbers registers t7 & t8. Specify this in the clobbers list when invoking bzero. Reported-by: James Hogan Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library function.") Cc: sta...@vger.kernel.org Signe

[PATCH 3/3] MIPS: memset.S: Reinstate delay slot indentation

convention for all instructions in a branch delay slot. This effectively reverts the above commit, plus other locations introduced with MIPSR6 support. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/lib/memset.S | 26 +- 1 file changed, 13 insertions(

[PATCH 3/3] MIPS: memset.S: Reinstate delay slot indentation

convention for all instructions in a branch delay slot. This effectively reverts the above commit, plus other locations introduced with MIPSR6 support. Signed-off-by: Matt Redfearn --- arch/mips/lib/memset.S | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --

[PATCH 1/3] MIPS: memset.S: Fix clobber of v1 in last_fixup

ould not be set is already contained in a2, the andi placing a value in v1 is not necessary and actively harmful in clobbering v1. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Reported-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <matt.redf

[PATCH 1/3] MIPS: memset.S: Fix clobber of v1 in last_fixup

ould not be set is already contained in a2, the andi placing a value in v1 is not necessary and actively harmful in clobbering v1. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Reported-by: James Hogan Signed-off-by: Matt Redfearn --- arch/mips/lib/memset.S | 2 +-

[PATCH v2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

Ci40 (MIPS32) and Cavium Octeon II (MIPS64). Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Suggested-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: - Use James Hogan's suggestion of replac

[PATCH v2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

Ci40 (MIPS32) and Cavium Octeon II (MIPS64). Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: sta...@vger.kernel.org Suggested-by: James Hogan Signed-off-by: Matt Redfearn --- Changes in v2: - Use James Hogan's suggestion of replacing t1 with a0 to get the correct remainde

Re: [PATCH 2/2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

Hi James, On 16/04/18 23:13, James Hogan wrote: On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote: The __clear_user function is defined to return the number of bytes that could not be cleared. From the underlying memset / bzero implementation this means setting register a2

Re: [PATCH 2/2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

Hi James, On 16/04/18 23:13, James Hogan wrote: On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote: The __clear_user function is defined to return the number of bytes that could not be cleared. From the underlying memset / bzero implementation this means setting register a2

Re: [PATCH 1/2] MIPS: memset.S: EVA & fault support for small_memset

Hi James, On 16/04/18 21:22, James Hogan wrote: On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote: @@ -260,6 +260,11 @@ jr ra andiv1, a2, STORMASK This patch looks good, well spotted! But whats that v1 write about? Any ideas? Seems to go

Re: [PATCH 1/2] MIPS: memset.S: EVA & fault support for small_memset

Hi James, On 16/04/18 21:22, James Hogan wrote: On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote: @@ -260,6 +260,11 @@ jr ra andiv1, a2, STORMASK This patch looks good, well spotted! But whats that v1 write about? Any ideas? Seems to go

[PATCH] MIPS: dts: Boston: Fix PCI bus dtc warnings:

bridge arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@1400: missing bus-range for PCI bridge Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/boot/dts/img/boston.dts | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/img/boston.

[PATCH] MIPS: dts: Boston: Fix PCI bus dtc warnings:

bridge arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@1400: missing bus-range for PCI bridge Signed-off-by: Matt Redfearn --- arch/mips/boot/dts/img/boston.dts | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img

[PATCH v2 6/6] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Chan

[PATCH v2 6/6] MIPS: perf: Fix BMIPS5000 system mode counting

oes not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn --- Changes in v2: New patch to

[PATCH v2 5/6] MIPS: perf: Fold vpe_id() macro into it's one last usage

set the counter to count the relevant VPE. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: Since BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. arch/mips/kernel/perf_event_mipsxx.c | 18 --

[PATCH v2 5/6] MIPS: perf: Fold vpe_id() macro into it's one last usage

set the counter to count the relevant VPE. Signed-off-by: Matt Redfearn --- Changes in v2: Since BMIPS5000 does not implement per TC counters, we can remove the check on cpu_has_mipsmt_pertccounters. arch/mips/kernel/perf_event_mipsxx.c | 18 -- 1 file changed, 4 insertions

[PATCH v2 4/6] MIPS: perf: Allocate per-core counters on demand

0.005179533 seconds time elapsed Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u 0.005179467 seconds time elapsed Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: - Fix !#ifdef C

[PATCH v2 4/6] MIPS: perf: Allocate per-core counters on demand

0.005179533 seconds time elapsed Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u 0.005179467 seconds time elapsed Signed-off-by: Matt Redfearn --- Changes in v2: - Fix !#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS

[PATCH v2 3/6] MIPS: perf: Fix perf with MT counting other threads

t -e instructions:u,branches:u ./test_prog Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: Fix mipsxx_pmu_enable_event for !#ifdef CONFIG_MIPS_

[PATCH v2 3/6] MIPS: perf: Fix perf with MT counting other threads

t -e instructions:u,branches:u ./test_prog Performance counter stats for './test_prog': 30002 instructions:u 1 branches:u Signed-off-by: Matt Redfearn --- Changes in v2: Fix mipsxx_pmu_enable_event for !#ifdef CONFIG_MIPS_MT_SMP arch/mips/kernel/perf_

[PATCH v2 2/6] MIPS: perf: Use correct VPE ID when setting up VPE tracing

Fix this by replacing smp_processor_id() with cpu_vpe_id(_cpu_data), in the vpe_id() macro, and pass vpe_id() to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also be removed since they no longer apply. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: None

[PATCH v2 2/6] MIPS: perf: Use correct VPE ID when setting up VPE tracing

Fix this by replacing smp_processor_id() with cpu_vpe_id(_cpu_data), in the vpe_id() macro, and pass vpe_id() to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also be removed since they no longer apply. Signed-off-by: Matt Redfearn --- Changes in v2: None arch/mips/ker

[PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

. A definition of this bit is added in mipsregs.h for MIPS Technologies. No other implementations support this feature. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- Changes in v2: None arch/mips/include/asm/mipsregs.h | 5 + arch/mips/kernel/perf_event_mipsxx.

  1   2   3   4   5   6   7   8   9   10   >