Hi Greg,
Please find my response inline.
> -Original Message-
> From: Greg KH
> Sent: Tuesday, April 20, 2021 2:21 PM
> To: Nava kishore Manne
> Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan
> ; Dragan Cvetic ;
> a...@arndb.de; Rajan Vaja ; Jolly
Hi Greg,
Please find my response inline.
> -Original Message-
> From: Greg KH
> Sent: Tuesday, April 20, 2021 2:18 PM
> To: Nava kishore Manne
> Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan
> ; Dragan Cvetic ;
> a...@arndb.de; Rajan Vaja ; Jolly
Hi Greg,
Please find my response inline.
> -Original Message-
> From: Greg KH
> Sent: Tuesday, April 20, 2021 2:17 PM
> To: Nava kishore Manne
> Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan
> ; Dragan Cvetic ;
> a...@arndb.de; Rajan Vaja ; Jolly
This patch adds zynqmp afi config driver.This is useful for
the configuration of the PS-PL interface on Zynq US+ MPSoC
platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig | 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynqmp-afi.c | 83
This patch adds the binding document for the zynqmp afi
config driver.
Signed-off-by: Nava kishore Manne
---
.../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++
1 file changed, 136 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi
This patch adds zynq afi config driver. This is useful for
the configuration of the PS-PL interface on zynq platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig| 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynq-afi.c | 81
This patch adds afi ioctl to support dynamic PS-PL
bus width settings.
Signed-off-by: Nava kishore Manne
---
drivers/firmware/xilinx/zynqmp.c | 13 +
include/linux/firmware/xlnx-zynqmp.h | 7 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/firmware/xilinx
This patch adds the binding document for the afi config
driver.
Signed-off-by: Nava kishore Manne
---
.../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
with the proper
Bus-width values
This patch series Adds afi config drivers support to handle the
PS-PL AXI port bus-width configurations.
Nava kishore Manne (5):
misc: doc: Add binding doc for the afi config driver
misc: zynq: Add afi config driver
firmware: xilinx: Add afi ioctl support
misc
Hi Moritz,
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Saturday, April 10, 2021 3:01 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.ker
Hi Rob,
Please find my response inline.
> -Original Message-
> From: Rob Herring
> Sent: Wednesday, March 10, 2021 10:50 PM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; Michal Simek ;
> gre...@linuxfoundation.org; Jolly Shah ; Rajan Vaja
Hi Moritz,
Thanks for providing the review comments.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Thursday, March 4, 2021 4:42 AM
> To: Moritz Fischer
> Cc: Nava kishore Manne ; t...@redhat.com;
> robh...@kernel.org; Mi
Hi Moritz,
Thanks for the response.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Friday, April 2, 2021 10:46 PM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Si
Adds support to handle FPGA/PL power Domain to optimize the PL power
consumption.
Nava kishore Manne (3):
dt-bindings: zynqmp: Add new PD_PL macro
fpga: region: Add fpga-region property 'power-domains'
fpga: region: Adds runtime PM support
.../devicetree/bindings/fpga/fpga-region.txt
Adds support to handle FPGA/PL power domain. With this patch,
the PL power domain will be turned on before loading the bitstream
and turned off while removing/unloading the bitstream using overlays.
This can be achieved by adding the runtime PM support.
Signed-off-by: Nava kishore Manne
Add fpga-region property 'power-domains' to allow to handle
the FPGA/PL power domins.
dt-bindings: fpga: Enable PM generic domain support
Signed-off-by: Nava kishore Manne
---
.../devicetree/bindings/fpga/fpga-region.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git
Add new power domain for PL region.
Signed-off-by: Nava kishore Manne
---
include/dt-bindings/power/xlnx-zynqmp-power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h
b/include/dt-bindings/power/xlnx-zynqmp-power.h
index 0d9a412fd5e0
Allows drivers to request the Configuration image
be loaded from dma-able continuous buffer to avoid
needless memory pressure and delays due to multiple
copies.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/zynqmp-fpga.c | 35 +++
1 file changed, 35
Add "fpga-config-from-dmabuf" property to allow the bitstream
configuration from pre-allocated dma-buffer.
Signed-off-by: Nava kishore Manne
---
Documentation/devicetree/bindings/fpga/fpga-region.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bin
.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/fpga-mgr.c | 126 +-
drivers/fpga/of-fpga-region.c | 3 +
include/linux/fpga/fpga-mgr.h | 6 +-
3 files changed, 132 insertions(+), 3 deletions(-)
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga
Nava kishore Manne (3):
fpga: region: Add fpga-region property 'fpga-config-from-dmabuf'
fpga: support loading from a pre-allocated buffer
fpga: zynqmp: Use the scatterlist interface
.../devicetree/bindings/fpga/fpga-region.txt | 2 +
drivers/fpga/fpga-mgr.c | 126
Hi Rob,
Thanks for providing the review comments.
Please find my response inline.
> -Original Message-
> From: Rob Herring
> Sent: Tuesday, March 9, 2021 1:50 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; Michal Simek ;
> gre...@linuxfou
Ping!
> -Original Message-
> From: Nava kishore Manne
> Sent: Thursday, February 11, 2021 10:42 AM
> To: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead
Ping!
> -Original Message-
> From: Nava kishore Manne
> Sent: Thursday, February 11, 2021 10:42 AM
> To: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
-Fixed file format and syntax issues.
Changes for v3:
-Removed
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
Changes for v2
This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Updated API Doc and commit msg
This series adds FPGA Manager support for the Xilinx
Versal chip.
Appana Durga Kedareswara rao (1):
dt-bindings: fpga: Add binding doc for versal fpga manager
Nava kishore Manne (2):
drivers: firmware: Add PDI load API support
fpga: versal-fpga: Add versal fpga manager driver
Ping!
> -Original Message-
> From: Nava kishore Manne
> Sent: Wednesday, January 27, 2021 2:43 PM
> To: Moritz Fischer
> Cc: t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infrad
Hi Rob,
Please find my response inline.
> -Original Message-
> From: Rob Herring
> Sent: Thursday, February 11, 2021 8:26 PM
> To: Nava kishore Manne
> Cc: linux-arm-ker...@lists.infradead.org; m...@kernel.org; linux-
> f...@vger.kernel.org; git ; Appana Dur
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
Changes for v2
This patch adds load PDI API support to enable PDI/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Nava kishore Manne
---
Changes for v2
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
-Fixed file format and syntax issues.
.../bindings/fpga/xlnx,versal-fpga.yaml
Appana Durga Kedareswara rao (1):
dt-bindings: fpga: Add binding doc for versal fpga manager
Nava kishore Manne (2):
drivers: firmware: Add PDI load API support
fpga: versal-fpga: Add versal fpga manager driver
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +
drivers/firmware
This patch Adds compatible value for Xilinx Dynamic Function eXchnage(DFX)
AXI Shutdown manager IP.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Modified the doc and added DFX axi shutdown manager node
example node as suggested by Tom Rix
are interrupted during reconfiguration.
PR-Decoupler and AXI shutdown manager are completely different IPs.
But both the IP registers are compatible and also both belong to the
same sub-system (fpga-bridge).So using same driver for both IP's.
Signed-off-by: Nava kishore Manne
---
Changes for v2
Nava kishore Manne (2):
dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown
manager
fpga: Add support for Xilinx DFX AXI Shutdown manager
.../bindings/fpga/xilinx-pr-decoupler.txt | 24 +++-
drivers/fpga/Kconfig | 9 -
drivers
Hi,
> -Original Message-
> From: Moritz Fischer
> Sent: Thursday, January 28, 2021 3:15 AM
> To: Michal Simek
> Cc: Nava kishore Manne ; Moritz Fischer
> ; t...@redhat.com; robh...@kernel.org; linux-
> f...@vger.kernel.org; devicet...@vger.kernel.
Hi Moritz,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Friday, January 22, 2021 10:47 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Si
Hi Moritz,
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Sunday, January 24, 2021 5:04 AM
> To: Nava kishore Manne
> Cc: Moritz Fischer ; t...@redhat.com;
> robh...@kernel.org; Michal Simek ; linux-
> f...@vge
Hi Moritz,
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Friday, January 22, 2021 10:45 AM
> To: Nava kishore Manne
> Cc: Moritz Fischer ; t...@redhat.com;
> robh...@kernel.org; Michal Simek ; linux-
> f...@vge
Hi Moritz,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Tuesday, January 19, 2021 6:03 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Si
Hi Michal,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Michal Simek
> Sent: Monday, January 18, 2021 2:22 PM
> To: Nava kishore Manne ; m...@kernel.org;
> t...@redhat.com; robh...@kernel.org; Michal Simek ;
> linux-f.
Hi Moritz,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Saturday, January 16, 2021 8:28 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Si
Hi Tom,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Tom Rix
> Sent: Friday, January 15, 2021 11:56 PM
> To: Nava kishore Manne ; m...@kernel.org;
> robh...@kernel.org; Michal Simek ; linux-
> f...@vger.k
Hi Tom,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Tom Rix
> Sent: Friday, January 15, 2021 11:37 PM
> To: Nava kishore Manne ; m...@kernel.org;
> robh...@kernel.org; Michal Simek ; linux-
> f...@vger.k
This commit adds secure BitStream Loading support for the Xilinx
ZynqMp chip.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/zynqmp-fpga.c | 8
include/linux/firmware/xlnx-zynqmp.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/fpga/zynqmp-fpga.c b
This commit adds secure flags to the framework to support
secure BitStream Loading.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/of-fpga-region.c | 10 ++
include/linux/fpga/fpga-mgr.h | 12
2 files changed, 22 insertions(+)
diff --git a/drivers/fpga/of-fpga-region.c
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++
1 file changed, 33 insertions(+)
create
This patch adds load pdi api support to enable pdi/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Nava kishore Manne
---
drivers/firmware
This patch adds driver for versal fpga manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
drivers/fpga/Kconfig
are interrupted during reconfiguration.
PR-Decoupler and AXI shutdown manager are completely different IPs.
But both the IP registers are compatible and also both belong to the
same sub-system (fpga-bridge).So using same driver for both IP's.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/xilinx
This patch Adds compatible value for Xilinx Dynamic Function eXchnage(DFX)
AXI Shutdown manager IP.
Signed-off-by: Nava kishore Manne
---
.../bindings/fpga/xilinx-pr-decoupler.txt | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/Documentation
Corrected typo
> -Original Message-
> From: Nava kishore Manne
> Sent: Monday, May 4, 2020 5:25 PM
> To: 'Moritz Fischer'
> Cc: Michal Simek ; linux-f...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gm
Hi Mortiz,
Thanks for proving the comments.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer [mailto:m...@kernel.org]
> Sent: Thursday, April 23, 2020 8:59 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; Michal Simek ; linux-
> f...@vger
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
---
Changes for v5:
-Removed hardcoded macro values and used BIT(x)
as suggested by Moritz.
drivers/fpga
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
Reviewed-by: Moritz Fischer
---
Changes for v5:
-Modified API's doc as suggested by Moritz.
drivers/firmware/xilinx/zynqmp.c | 45
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
Acked-by: Alan Tull
Acked-by: Moritz Fischer
---
Changes for v5:
-None.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
1 file
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager support for Xilinx zynqmp
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
drivers/firmware/xilinx/zynqmp.c | 45
Hi Moritz,
Thanks for the quick response.
Please find my response inline
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Tuesday, April 9, 2019 12:04 PM
> To: Moritz Fischer ; Nava kishore Manne
>
> Cc: at...@kernel.org; robh...@ker
Hi Alan,
Thanks for the response.
Please find my response inline.
> -Original Message-
> From: Alan Tull [mailto:at...@kernel.org]
> Sent: Tuesday, April 9, 2019 1:57 AM
> To: Moritz Fischer
> Cc: Michal Simek ; Nava kishore Manne
> ; Rob Herring ; Mark Rutland
>
age-
> From: Alan Tull [mailto:at...@kernel.org]
> Sent: Tuesday, April 2, 2019 11:57 PM
> To: Nava kishore Manne
> Cc: Moritz Fischer ; Rob Herring ; Mark
> Rutland ; Michal Simek ; Rajan
> Vaja ; Jolly Shah ; linux-
> f...@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENE
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-Updated the Fpga Mgr registrations call's
to 5.0
-Removed dma_set_mask_and_coherent() As the FW
supports only
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-None.
Chnages for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
Acked-by: Alan Tull
Acked-by: Moritz Fischer
---
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
1 file changed, 25 insertions(+)
create mode
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager support for Xilinx zynqmp
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
drivers/firmware/xilinx/zynqmp.c | 46
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v5:
-Moved pcap node as a child to firwmare
node as suggested by Rob.
Changes for v4:
-Modified binding description as suggested
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP pin controller
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++
1 file changed, 275 insertions(+)
create mode
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2
From: Rajan Vaja
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/power/xlnx,zynqmp-genpd.txt | 34
include/dt-bindings/power/xlnx-zynqmp-power.h | 39
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../power/reset/xlnx,zynqmp-power.txt | 25 +++
1 file changed, 25 insertions(+)
create mode
= "MIO19";
bias-disable;
schmitt-cmos = ;
};
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zy
Hi Rob,
Thanks for the response.
Please find my response inline.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, March 26, 2019 12:49 AM
> To: Nava kishore Manne
> Cc: at...@kernel.org; m...@kernel.org; mark.rutl...@arm.co
Ping!!
> -Original Message-
> From: Nava kishore Manne [mailto:nava.ma...@xilinx.com]
> Sent: Thursday, March 14, 2019 7:31 PM
> To: at...@kernel.org; m...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; Jolly Shah ; Nava kishore
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP pin controller
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++
1 file changed, 275 insertions(+)
create mode
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-Modified binding description as suggested by Moritz Fischer.
Changes for v3:
-Removed PCAP as a child node to the FW and Created
From: Rajan Vaja
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/power/xlnx,zynqmp-genpd.txt | 34
include/dt-bindings/power/xlnx-zynqmp-power.h | 39
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2
io-standard = ;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../power/reset/xlnx,zynqmp-power.txt | 25 +++
1 file changed, 25 insertions(+)
create mode
Ping !!
> -Original Message-
> From: Nava kishore Manne
> Sent: Tuesday, March 5, 2019 3:12 PM
> To: 'Rob Herring'
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; devicet...@vger.k
Hi Rob,
Thanks for the quick response.
Please find my response inline.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Monday, March 4, 2019 10:57 PM
> To: Nava kishore Manne
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
&g
Hi Rob,
Thanks for providing the review comments..
Please find my response inline.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaj
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Removed "" separators.
Chan
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Fixed some minor coding issues as suggested
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Chnages for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Added Firmware FPGA Manager
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager support for Xilinx zynqmp
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt| 13 ++
drivers/firmware/xilinx/zynqmp.c | 46
This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-None.
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3
This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Removed irrelevant changes from Kconfig and
Make files.
Changes for v2:
-None
Nava kishore Manne (3):
firmware: xilinx: Add zynqmp_pm_get_chipid() API
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
nvmem: zynqmp: Added zynqmp nvmem firmware driver
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 ++
drivers/firmware/xilinx/zynqmp.c
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings
This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-Changed nvmem_register
Nava kishore Manne (3):
firmware: xilinx: Add zynqmp_pm_get_chipid() API
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
nvmem: zynqmp: Added zynqmp nvmem firmware driver
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 ++
drivers/firmware/xilinx/zynqmp.c
This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-corrected typo error in commit msg
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Fixed some minor coding issues as suggested
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2
Nava kishore Manne (3):
firmware: xilinx: Add reset API's
dt-bindings: reset: Add bindings for ZynqMP reset driver
reset: reset-zynqmp: Adding support for Xilinx zynqmp reset
controller.
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
drivers/firmware/xilinx/zynqmp.c
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