-by: Paul Cercueil
Cheers,
-Paul
---
Notes:
v6:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c
b/drivers/pinctrl/pinctrl-ingenic.c
index 8ed62a4..b57433d 100644
--- a/drivers/pinctrl
l set)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
@@ -2668,7 +3131,7 @@ static inline void
jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
}
static inline bool ingenic_get_pin_config(struct ingenic_pinctrl
*jzpc,
-
Hi Zhou,
Le sam. 17 avril 2021 à 0:14, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
Notes:
v3:
New
Hi Zhou,
Le sam. 17 avril 2021 à 0:14, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
Notes:
v3:
New
im, 0),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+ INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+ INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
Missing lcd-24bit, but it can always be added later.
Reviewed-by: Pa
trl/pinctrl-ingenic.c
index 009901b..4c48250 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -3,8 +3,8 @@
* Ingenic SoCs pinctrl driver
*
* Copyright (c) 2017 Paul Cercueil
- * Copyright (c) 2019 周琰杰 (Zhou Yanjie)
* Copyright (c) 2017, 2019 Paul
and
the
data[1:0] has not been connected. And according to the description,
the two interfaces supported by X1830 are respectively referred to
as
"TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is
replaced
with "lcd-tft-xxx&qu
Hi Neil,
Le mer. 14 avril 2021 à 8:17, Neil Armstrong
a écrit :
Hi,
Le 13/04/2021 à 22:56, Paul Cercueil a écrit :
Hi Neil,
I get build failures locally:
drivers/gpu/drm/bridge/ite-it66121.c: In function
‘it66121_hw_reset’:
drivers/gpu/drm/bridge/ite-it66121.c:242:2: error: implicit
Le mer. 14 avril 2021 à 8:17, Neil Armstrong
a écrit :
Hi,
Le 13/04/2021 à 22:56, Paul Cercueil a écrit :
Hi Neil,
I get build failures locally:
drivers/gpu/drm/bridge/ite-it66121.c: In function
‘it66121_hw_reset’:
drivers/gpu/drm/bridge/ite-it66121.c:242:2: error: implicit
Hi Neil,
I get build failures locally:
drivers/gpu/drm/bridge/ite-it66121.c: In function
‘it66121_hw_reset’:
drivers/gpu/drm/bridge/ite-it66121.c:242:2: error: implicit declaration
of function ‘gpiod_set_value’
[-Werror=implicit-function-declaration]
242 | gpiod_set_value(ctx->gpio_reset,
Hi Neil,
Le lun. 12 avril 2021 à 17:46, Neil Armstrong
a écrit :
From: Phong LE
Add the ITE bridge HDMI it66121 bindings.
Signed-off-by: Phong LE
Signed-off-by: Neil Armstrong
---
.../bindings/display/bridge/ite,it66121.yaml | 123
++
1 file changed, 123 insertions(+)
Hi,
Can I have an ACK for this patch?
Then I can apply it to drm-misc-next-fixes.
Cheers,
-Paul
Le mar. 23 mars 2021 à 14:40, Paul Cercueil a
écrit :
When using a 24-bit panel on a 8-bit serial bus, the pixel clock
requested by the panel has to be multiplied by 3, since the subpixels
Can I have an ACK for this patch?
Cheers,
-Paul
Le lun. 29 mars 2021 à 18:50, Paul Cercueil a
écrit :
Avoid requesting a full modeset if the sharpness property is not
modified, because then we don't actually need it.
Fixes: fc1acf317b01 ("drm/ingenic: Add support for the IPU")
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 507d8c5a418a5d413bf9751d4ff94b259e947736
Gitweb:
https://git.kernel.org/tip/507d8c5a418a5d413bf9751d4ff94b259e947736
Author:Paul Cercueil
AuthorDate:Mon, 08 Mar 2021 21:23:00
Committer
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8a3f717f35a3e9a28a935f8e4459c72ba00e90ca
Gitweb:
https://git.kernel.org/tip/8a3f717f35a3e9a28a935f8e4459c72ba00e90ca
Author:Paul Cercueil
AuthorDate:Mon, 08 Mar 2021 21:23:01
Committer
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 352408aff91d06fd2f0e35d52079bd0cd70cd29e
Gitweb:
https://git.kernel.org/tip/352408aff91d06fd2f0e35d52079bd0cd70cd29e
Author:Paul Cercueil
AuthorDate:Mon, 08 Mar 2021 21:23:02
Committer
Le ven. 9 avril 2021 à 17:30, Masahiro Yamada a
écrit :
On Fri, Apr 9, 2021 at 5:15 PM Paul Cercueil
wrote:
Hi Masahiro,
Le ven. 9 avril 2021 à 5:58, Masahiro Yamada
a
écrit :
> is included from all the kernel-space source
files,
> including C, assembly, linker s
Hi Masahiro,
Le ven. 9 avril 2021 à 5:58, Masahiro Yamada a
écrit :
is included from all the kernel-space source files,
including C, assembly, linker scripts. It is intended to contain
minimal
set of macros to evaluate CONFIG options.
IF_ENABLED() is an intruder here because (x ? y : z)
pport for the IPU")
Cc: # 5.8+
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 11 +--
drivers/gpu/drm/ingenic/ingenic-ipu.c | 2 +-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/d
s modified.
Cheers,
-Paul
Paul Cercueil (2):
drm/ingenic: Switch IPU plane to type OVERLAY
drm/ingenic: Don't request full modeset if property is not modified
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 11 +--
drivers/gpu/drm/ingenic/ingenic-ipu.c | 6 --
2 files changed, 9
It should have been an OVERLAY from the beginning. The documentation
stipulates that there should be an unique PRIMARY plane per CRTC.
Fixes: fc1acf317b01 ("drm/ingenic: Add support for the IPU")
Cc: # 5.8+
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-
Avoid requesting a full modeset if the sharpness property is not
modified, because then we don't actually need it.
Fixes: fc1acf317b01 ("drm/ingenic: Add support for the IPU")
Cc: # 5.8+
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-ipu.c | 4 +++-
1 file
Le lun. 29 mars 2021 à 15:42, Simon Ser a écrit
:
On Monday, March 29th, 2021 at 5:39 PM, Paul Cercueil
wrote:
Ok, I read that as "all drivers should provide AT LEAST one primary
plane per CRTC", and not as "all drivers should provide ONE AND ONLY
ONE primary plane pe
Le dim. 28 mars 2021 à 1:05, Laurent Pinchart
a écrit :
Hi Paul,
Thank you for the patch.
On Sat, Mar 27, 2021 at 11:57:41AM +, Paul Cercueil wrote:
This performs the same operation as drmm_encoder_alloc(), but
only allocates and returns a struct drm_encoder instance.
v4: Rename
Le lun. 29 mars 2021 à 17:35, Maxime Ripard a
écrit :
On Mon, Mar 29, 2021 at 04:15:28PM +0100, Paul Cercueil wrote:
Hi Maxime,
Le lun. 29 mars 2021 à 16:07, Maxime Ripard a
écrit :
> On Sat, Mar 27, 2021 at 11:22:14AM +0000, Paul Cercueil wrote:
> > The ingenic-drm drive
Hi Simon,
Le lun. 29 mars 2021 à 14:11, Simon Ser a écrit
:
On Monday, March 29th, 2021 at 4:07 PM, Maxime Ripard
wrote:
Since it looks like you have two mutually exclusive planes, just
expose
one and be done with it?
You can expose the other as an overlay. Clever user-space will be
Le lun. 29 mars 2021 à 17:35, Pekka Paalanen a
écrit :
On Mon, 29 Mar 2021 12:41:00 +0100
Paul Cercueil wrote:
Hi,
Le lun. 29 mars 2021 à 11:15, Pekka Paalanen
a
écrit :
> On Sat, 27 Mar 2021 11:26:26 +
> Paul Cercueil wrote:
>
>> It has two mutually exclu
Hi Maxime,
Le lun. 29 mars 2021 à 16:07, Maxime Ripard a
écrit :
On Sat, Mar 27, 2021 at 11:22:14AM +, Paul Cercueil wrote:
The ingenic-drm driver has two mutually exclusive primary planes
already; so the fact that a CRTC must have one and only one primary
plane is an invalid
Hi,
Le lun. 29 mars 2021 à 11:15, Pekka Paalanen a
écrit :
On Sat, 27 Mar 2021 11:26:26 +
Paul Cercueil wrote:
It has two mutually exclusive background planes (same Z level) + one
overlay plane.
What's the difference between the two background planes?
How will generic userspace
Hi Zhou,
Le jeu. 25 mars 2021 à 17:03, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/23 上午2:39, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou
Hi Zhou,
Le jeu. 25 mars 2021 à 16:38, Zhou Yanjie
a écrit :
Hi,
On 2021/3/23 上午2:24, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie
: Use the new drmm_plain_simple_encoder_alloc() macro
v4: Use drmm_plain_encoder_alloc() macro
Fixes: c369cb27c267 ("drm/ingenic: Support multiple panels/bridges")
Cc: # 5.8+
Signed-off-by: Paul Cercueil
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/ingenic/ingenic-drm-
he panel wrapper from the
lvds-encoder bridge.")
Cc: # 4.12+
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Signed-off-by: Paul Cercueil
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/panel.c | 12
1 file changed,
Cheers,
-Paul
Paul Cercueil (3):
drm: bridge/panel: Cleanup connector on bridge detach
drm/encoder: Add macro drmm_plain_encoder_alloc()
drm/ingenic: Register devm action to cleanup encoders
drivers/gpu/drm/bridge/panel.c| 12
drivers/gpu/drm/ingenic/ingenic-drm
This performs the same operation as drmm_encoder_alloc(), but
only allocates and returns a struct drm_encoder instance.
v4: Rename macro drmm_plain_encoder_alloc() and move to
. Since it's not "simple" anymore it
will now take funcs/name arguments as well.
Signed-off-by: Pau
It has two mutually exclusive background planes (same Z level) + one
overlay plane.
-Paul
Le sam. 27 mars 2021 à 11:24, Simon Ser a écrit
:
On Saturday, March 27th, 2021 at 12:22 PM, Paul Cercueil
wrote:
The ingenic-drm driver has two mutually exclusive primary planes
already; so
The ingenic-drm driver has two mutually exclusive primary planes
already; so the fact that a CRTC must have one and only one primary
plane is an invalid assumption.
Fixes: 96962e3de725 ("drm: require each CRTC to have a unique primary plane")
Cc: # 5.11
Signed-off-by: Paul Cercueil
--
Le mer. 24 févr. 2021 à 13:44, Paul Cercueil a
écrit :
Hi,
Some feedback for patches 1-3? Laurent?
1-month anniversary ping :)
Cheers,
-Paul
Cheers,
-Paul
Le dim. 24 janv. 2021 à 8:55, Paul Cercueil a
écrit :
Hi,
Here are three independent fixes. The first one addresses a
use
Hi Zhou,
Le mar. 23 mars 2021 à 23:41, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/23 上午1:40, Paul Cercueil wrote:
Hi Zhou,
Le mer. 17 mars 2021 à 20:41, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Add the CGU code and the compatible string to the TCU driver
t_rate()
used crtc_state->adjusted_mode->clock instead.
Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when using a
3x8-bit panel")
Cc: sta...@vger.kernel.org # v5.10
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +-
1 file changed, 1 in
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 502
+-
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 259
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 132
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 137
/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -3,8 +3,8 @@
* Ingenic SoCs pinctrl driver
*
* Copyright (c) 2017 Paul Cercueil
- * Copyright (c) 2019 周琰杰 (Zhou Yanjie)
* Copyright (c) 2017, 2019 Paul Boddie
+ * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie)
*/
#include
ins.
The JZ4750,
+ the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
ports, PA
+ to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
PA to PG,
+ for a total of 224 pins.
While we're at it, the JZ4725B has also 4 GPIO ports.
maintainers:
- Paul Cercueil
idxh = pin % half * 2;
I had to look up operator precedence in C, '*' and '%' have the same
priority so this reads left-to-right.
I'd suggest adding parentheses around the '%' to make it more obvious.
With that:
Reviewed-by: Paul Cercueil
Cheers,
-Paul
+
+ if (idx < half)
+
n an older kernel (than the
one in -rc phase). Therefore you need to Cc linux-stable. Like this:
Cc: # v5.0
Signed-off-by: 周琰杰 (Zhou Yanjie)
With that said:
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
Notes:
v2:
New patch.
v2->v3:
Add fixes tag.
drivers/pi
Hi Zhou,
Le mer. 17 mars 2021 à 20:41, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Add the CGU code and the compatible string to the TCU driver to
support
the JZ4760 SoC.
Signed-off-by: Paul Cercueil
---
drivers/clk/ingenic/Kconfig| 10
LLVM's ld.lld chokes on the 64-bit sign-extended load addresses. Use
32-bit addresses if the linker is LLVM's ld.lld.
Signed-off-by: Paul Cercueil
---
arch/mips/generic/Platform | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/generic/Platform b/arch/mips
nt from 8 bytes
back to STRUCT_ALIGNMENT bytes in vmlinux.lds.S.
Fixes: 6654111c893f ("MIPS: vmlinux.lds.S: align raw appended dtb to 8 bytes")
Cc: Bjørn Mork
Signed-off-by: Paul Cercueil
---
arch/mips/kernel/vmlinux.lds.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ar
Hi Thomas,
Le lun. 15 mars 2021 à 8:43, Thomas Zimmermann a
écrit :
Hi
Am 11.03.21 um 13:33 schrieb Paul Cercueil:
Le jeu. 11 mars 2021 à 12:28, Christoph Hellwig
a écrit :
On Sun, Mar 07, 2021 at 08:28:34PM +, Paul Cercueil wrote:
+drm_atomic_for_each_plane_damage
Hi Stephen,
Le sam. 13 mars 2021 à 14:28, Stephen Boyd a écrit
:
Quoting Paul Cercueil (2021-03-07 09:07:41)
The purpose of this function is to be used along with the notifier
mechanism.
When a parent clock can see its rate externally changed at any
moment,
and a driver needs
trl driver
*
* Copyright (c) 2017 Paul Cercueil
- * Copyright (c) 2019 周琰杰 (Zhou Yanjie)
* Copyright (c) 2017, 2019 Paul Boddie
+ * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie)
*/
#include
@@ -29,6 +29,17 @@
#define GPIO_PIN 0x00
#define GPIO_
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition
section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Che
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
Notes:
v2:
New patch.
drivers/pinctrl
Hi Zhou,
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Signed-off-by: 周琰杰 (Zhou Yanjie)
This is a fix, so it needs a Fixes: tag, and you need to Cc
linux-stable.
---
Hi,
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Signed-off-by: 周琰杰 (Zhou Yanjie)
No Fixes: tag?
And if the bug wasn't introduced in 5.12-rc1 you'll need to Cc
linux-stable as well.
---
Le jeu. 11 mars 2021 à 12:36, Christoph Hellwig a
écrit :
On Thu, Mar 11, 2021 at 12:32:27PM +, Paul Cercueil wrote:
> dma_to_phys must not be used by drivers.
>
> I have a proper helper for this waiting for users:
>
>
http://git.infradead.org/users/hch/misc
Le jeu. 11 mars 2021 à 12:30, Christoph Hellwig a
écrit :
On Sun, Mar 07, 2021 at 08:28:35PM +, Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
possible
to specify that we want GEM buffers backed by non-coherent memory.
Shouldn't there be a way
Le jeu. 11 mars 2021 à 12:28, Christoph Hellwig a
écrit :
On Sun, Mar 07, 2021 at 08:28:34PM +, Paul Cercueil wrote:
+ drm_atomic_for_each_plane_damage(, ) {
+ for (i = 0; i < finfo->num_planes; i++) {
+ daddr = drm_fb_cma_get_gem_addr
Hi Christoph,
Le jeu. 11 mars 2021 à 12:26, Christoph Hellwig a
écrit :
+int drm_gem_cma_mmap_noncoherent(struct drm_gem_object *obj,
+ struct vm_area_struct *vma)
+{
+ struct drm_gem_cma_object *cma_obj;
+ unsigned long pfn;
+ int ret;
+
+
Le jeu. 11 mars 2021 à 10:27, Hillf Danton a écrit
:
On Wed, 10 Mar 2021 19:01:01 + Paul Cercueil wrote:
Le lun. 8 mars 2021 11:47, Hillf Danton a crit :
On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers
.
Is that a new addition? That severely reduces the patchset size, which
is perfect.
I'll send a V3 then.
Cheers,
-Paul
And in the long run, we could try to consolidate all drivers/helpers
mapping flags in struct drm_gem_object.
Best regards
Thomas
Am 07.03.21 um 21:28 schrieb Paul Cercueil
Hi Hillf,
Le lun. 8 mars 2021 à 11:47, Hillf Danton a écrit :
On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
possible
to specify that we want GEM buffers backed by non-coherent memory.
This dramatically speeds up
Le mer. 10 mars 2021 à 16:03, Andy Shevchenko
a écrit :
On Tue, Mar 9, 2021 at 6:42 PM 周琰杰 (Zhou Yanjie)
wrote:
1.Add tabs before values to align the code in the macro definition
section.
2.Fix bugs related to the MAC of JZ4770, add missing pins to the
MII group.
3.Adjust the
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 673433e7c288927f7244658788f203c660d7a6f6
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/673433e7c288927f7244658788f203c660d7a6f6
Author:Paul Cercueil
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 5fbecd2389f48e1415799c63130d0cdce1cf3f60
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/5fbecd2389f48e1415799c63130d0cdce1cf3f60
Author:Paul Cercueil
Add support for the TCU (Timer/Counter Unit) of the JZ4760 and JZ4760B
SoCs.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
drivers/clocksource/ingenic-timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/ingenic-timer.c
b/drivers/clocksource/ingenic
The OST in the JZ4760B SoC works exactly the same as in the JZ4770. But
since the JZ4760B is older, its Device Tree string does not fall back to
the JZ4770 one; so add support for the JZ4760B compatible string here.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
drivers/clocksource
-off-by: Paul Cercueil
---
Notes:
v2: - Fix indentation
- Fix example not using correct compatible strings
.../bindings/timer/ingenic,tcu.yaml | 30 ++-
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer
Le lun. 8 mars 2021 à 10:39, Rob Herring a écrit :
On Sun, 07 Mar 2021 17:15:51 +, Paul Cercueil wrote:
Add compatible strings to support the system timer, clocksource,
OST,
watchdog and PWM blocks of the JZ4760 and JZ4760B SoCs.
Newer SoCs which behave like the JZ4760 or JZ4760B
Le dim. 7 mars 2021 à 17:07, Paul Cercueil a
écrit :
The main PLL can have its rate changed at any moment. To keep the MMC
clock running at a rate that fits the specifications, we need to
recompute the MMC clock rate every time the PLL rate changes.
Use a mutex to ensure that the MMC
ach of using a jiffies-based timer is taken.
Signed-off-by: Paul Cercueil
---
Notes:
v2: HRTIMER_MODE_REL_SOFT -> HRTIMER_MODE_REL
v3: Only use a hrtimer-based timer if we know that reading the GPIO
will never sleep.
drivers/input/keyboard/gpio_keys.
of the standard
timer to address this issue.
Note that by using a hard IRQ for the hrtimer callback, we can get rid
of the spin_lock_irqsave() and spin_unlock_irqrestore().
Signed-off-by: Paul Cercueil
---
Notes:
v2-v3: No change
drivers/input/keyboard/gpio_keys.c | 27
The input_sync() function is already called after the loop in
gpio_keys_report_state(), so it does not need to be called after each
iteration within gpio_keys_gpio_report_event().
Signed-off-by: Paul Cercueil
---
Notes:
v2: Keep the input_sync() within gpio_keys_report_state() so that it's
Hi Dmitry,
Le dim. 7 mars 2021 à 12:20, Dmitry Torokhov
a écrit :
On Fri, Mar 05, 2021 at 08:00:43PM +, Paul Cercueil wrote:
Hi Dmitry,
Le ven. 5 mars 2021 à 10:35, Dmitry Torokhov
a
écrit :
> Hi Paul,
>
> On Fri, Mar 05, 2021 at 05:01:11PM +0000, Paul Cercu
This function can be used by drivers that use damage clips and have
CMA GEM objects backed by non-coherent memory. Calling this function
in a plane's .atomic_update ensures that all the data in the backing
memory have been written to RAM.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm
).
Leave it disabled by default, since it is specific to one use-case
(software rendering).
v2: Rework code to work with new DRM APIs regarding plane states
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 49 ++-
drivers/gpu/drm/ingenic/ingenic-drm.h
buffer with
the write-combine cache attribute set. This is the case for instance on
some Ingenic SoCs.
v2: Add inline doc about why we need this, and improve commit message
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 76 +---
include/drm
This function can be used by drivers that need to mmap dumb buffers
created with non-coherent backing memory.
v2: Use dma_to_phys() since cma_obj->paddr isn't a phys_addr_t but a
dma_addr_t.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c |
This function can be used by drivers to create dumb buffers with
non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 37 +---
include/drm/drm_gem_cma_helper.h | 5
2 files changed, 38 insertions(+), 4 deletions
urth patch adds a function to be used with the damage helpers.
Finally, the last patch adds support for non-coherent GEM buffers to the
ingenic-drm driver. The functionality is enabled through a module
parameter, and is disabled by default.
Cheers,
-Paul
Paul Cercueil (5):
drm: Add and expor
, this is not a
bugfix, but we should nonetheless remove that property from the example
to match the documentation.
Signed-off-by: Paul Cercueil
---
.../bindings/display/panel/kingdisplay,kd035g6-54nt.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings
, this is not a
bugfix, but we should nonetheless remove that property to match the
documentation.
Signed-off-by: Paul Cercueil
---
arch/mips/boot/dts/ingenic/gcw0.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts
b/arch/mips/boot/dts/ingenic/gcw0.dts
index
of the standard
timer to address this issue.
Note that by using a hard IRQ for the hrtimer callback, we can get rid
of the spin_lock_irqsave() and spin_unlock_irqrestore().
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
drivers/input/keyboard/gpio_keys.c | 27
key is quickly pressed then released (on a human's time
scale).
Switching to hrtimers fixes this issue, and will work even on extremely
low HZ values (tested at HZ=24).
Signed-off-by: Paul Cercueil
---
Notes:
v2: HRTIMER_MODE_REL_SOFT -> HRTIMER_MODE_REL
drivers/input/keyboard/gpio_keys.
The input_sync() function is already called after the loop in
gpio_keys_report_state(), so it does not need to be called after each
iteration within gpio_keys_gpio_report_event().
Signed-off-by: Paul Cercueil
---
Notes:
v2: Keep the input_sync() within gpio_keys_report_state() so that it's
Add the ingenic,jz4760b-intc compatible string with a fallback to the
ingenic,jz4760-intc compatible string.
Signed-off-by: Paul Cercueil
---
.../devicetree/bindings/interrupt-controller/ingenic,intc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings
Add support for the interrupt controller found in the JZ4760 SoC, which
works exactly like the one in the JZ4770.
Signed-off-by: Paul Cercueil
---
Notes:
Note that the binding documentation for the ingenic,jz4760-tcu
compatible string has been submitted in a different patchset
The OST in the JZ4760B SoC works exactly the same as in the JZ4770. But
since the JZ4760B is older, its Device Tree string does not fall back to
the JZ4770 one; so add support for the JZ4760B compatible string here.
Signed-off-by: Paul Cercueil
---
drivers/clocksource/ingenic-ost.c | 5 +++--
1
Add support for the TCU (Timer/Counter Unit) of the JZ4760 and JZ4760B
SoCs.
Signed-off-by: Paul Cercueil
---
drivers/clocksource/ingenic-timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/ingenic-timer.c
b/drivers/clocksource/ingenic-timer.c
index 905fd6b163a8
-off-by: Paul Cercueil
---
.../bindings/timer/ingenic,tcu.yaml | 28 ++-
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
index 024bcad75101
change will happen when we know that the controller is not in
use.
Cheers,
-Paul
Paul Cercueil (2):
clk: Add clk_get_first_to_set_rate
mmc: jz4740: Add support for monitoring PLL clock rate changes
drivers/clk/clk.c | 9 +
drivers/mmc/host/jz4740_mmc.c | 70
.
For that reason, we need to register the notifier on the parent clock of
the first ancestor of the base clock that will effectively modify its
rate when clk_set_rate() is called, which we can now obtain with
clk_get_first_to_set_rate().
Signed-off-by: Paul Cercueil
---
drivers/clk/clk.c | 9
-off-by: Paul Cercueil
---
drivers/mmc/host/jz4740_mmc.c | 70 ++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index b3c636edbb46..1197b8c6b6ed 100644
--- a/drivers/mmc/host/jz4740_mmc.c
Le dim. 7 mars 2021 à 14:30, Russell King - ARM Linux admin
a écrit :
On Sun, Mar 07, 2021 at 02:29:07PM +, Paul Cercueil wrote:
Hi,
Le dim. 7 mars 2021 à 14:27, Russell King - ARM Linux admin
a écrit :
> On Sun, Mar 07, 2021 at 02:06:26PM +0000, Paul Cercueil wr
Signed-off-by: Wei Yongjun
Acked-by: Paul Cercueil
Cheers,
-Paul
---
drivers/phy/ingenic/phy-ingenic-usb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/ingenic/phy-ingenic-usb.c
b/drivers/phy/ingenic/phy-ingenic-usb.c
index ea127b177f46..28c28d816
Le dim. 7 mars 2021 à 15:21, Tang Bin a
écrit :
The function devm_platform_ioremap_resource has already contained
error message if failed, so remove superfluous dev_err here.
Signed-off-by: Zhang Shengju
Signed-off-by: Tang Bin
Looks good.
Acked-by: Paul Cercueil
Cheers,
-Paul
Hi,
Le dim. 7 mars 2021 à 14:27, Russell King - ARM Linux admin
a écrit :
On Sun, Mar 07, 2021 at 02:06:26PM +, Paul Cercueil wrote:
On error, or when the passed parameter is NULL, the return value is
NULL
and not a PTR_ERR()-encoded value.
No, the documentation is accurate. The CCF
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