Hi Quan,
On Tue, Mar 30, 2021 at 09:10:28PM +0700, Quan Nguyen wrote:
> The SMBus system interface (SSIF) IPMI BMC driver can be used to perform
> in-band IPMI communication with their host in management (BMC) side.
>
> This commits adds support specifically for Aspeed AST2500 which commonly
>
On Thu, Apr 01, 2021 at 06:26:07PM +0800, Yang Yingliang wrote:
> There is an error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
>
> Reported-by: Hulk Robot
> Signed-off-by: Yang Yingliang
Thank you,
Reviewed
On Fri, Mar 26, 2021 at 03:26:15PM +0100, Benjamin Gaignard wrote:
>
> Le 26/03/2021 à 15:11, Philipp Zabel a écrit :
> > On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
> > > Introducing G2 hevc video decoder lead to modify the bindings to allow
> >
On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote:
> Split VPU node in two: one for G1 and one for G2 since they are
> different hardware blocks.
> Add syscon for hardware control block.
> Remove reg-names property that is useless.
> Each VPU node only need one interrupt.
>
>
Benjamin Gaignard
Reviewed-by: Philipp Zabel
regards
Philipp
clocks, vpu->clocks);
>
> @@ -150,8 +149,22 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void
> *dev_id)
>
> static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
> {
> - vpu->dec_base = vpu->reg_bases[0];
> - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
> + struct device_node *np = vpu->dev->of_node;
> +
> + vpu->ctrl_base = syscon_regmap_lookup_by_phandle(np,
> "nxp,imx8mq-vpu-ctrl");
I think calling this nxp,imx8m-vpu-ctrl would allow to share this with
i.MX8MM later. Otherwise,
Reviewed-by: Philipp Zabel
thanks
Philipp
On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
> Introducing G2 hevc video decoder lead to modify the bindings to allow
> to get one node per VPUs.
> VPUs share one hardware control block which is provided as a phandle on
> an syscon.
> Each node got now one reg and one
On Thu, Mar 25, 2021 at 10:03:23AM +0800, Liu Ying wrote:
> On Wed, 2021-03-24 at 17:47 +0100, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > When CONFIG_OF is disabled, building with 'make W=1' produces warnings
> > about out of bounds array access:
> >
> > drivers/gpu/drm/imx/imx-ldb.c:
On Mon, Mar 22, 2021 at 10:56:40AM +0800, Liu Ying wrote:
> LDB channel1 should be registered if it is the only channel to be used.
> Without this patch, imx_ldb_bind() would skip registering LDB channel1
> if LDB channel0 is not used, no matter LDB channel1 needs to be used or
> not.
>
> Fixes:
On Wed, Jan 20, 2021 at 01:16:08AM -0800, Pan Bian wrote:
> Put DRM device on initialization failure path rather than directly
> return error code.
>
> Fixes: a67d5088ceb8 ("drm/imx: drop explicit drm_mode_config_cleanup")
> Signed-off-by: Pan Bian
Thank you, applied to imx-drm/fixes.
regards
Hi Cristian,
On Thu, Mar 11, 2021 at 03:20:13AM +0200, Cristian Ciocaltea wrote:
> Add new driver for the Ethernet MAC used on the Actions Semi Owl
> family of SoCs.
>
> Currently this has been tested only on the Actions Semi S500 SoC
> variant.
>
> Signed-off-by: Cristian Ciocaltea
> ---
On Thu, 2021-03-04 at 17:03 +0100, Michal Simek wrote:
>
> On 3/4/21 5:00 PM, Philipp Zabel wrote:
> > Fixes checkpatch issues:
> >
> > ERROR: code indent should use tabs where possible
> > #86: FILE: drivers/reset/reset-zynqmp.c:86:
> > +.reset
FIPS 140-2(2001-10-10) Continuous run: 0
> rngtest: input channel speed: (min=37.253; avg=320.827; max=635.783)Mibits/s
> rngtest: FIPS tests speed: (min=12.141; avg=15.034; max=16.428)Mibits/s
> rngtest: Program run time: 1336176 microseconds
>
> Signed-off-by: Álvaro Fernández Rojas
reset-axs10x is GPL-2.0-only, add a SPDX-License-Identifier.
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-axs10x.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c
index a854ef41364d..ca78b859936c 100644
Fixes a checkpatch warning:
WARNING: It's generally not useful to have the filename in the file
#3: FILE: drivers/reset/reset-oxnas.c:3:
+ * drivers/reset/reset-oxnas.c
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-oxnas.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
) \
+ container_of(rcdev, struct ti_syscon_reset_data, rcdev)
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-ti-syscon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 218370faf37b
Fixes a checkpatch error:
ERROR: Macros with complex values should be enclosed in parentheses
#23: FILE: drivers/reset/reset-uniphier.c:23:
+#define UNIPHIER_RESET_ID_END(unsigned int)(-1)
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-uniphier.c | 2 +-
1 file
Fixes a checkpatch warning:
WARNING: Possible comma where semicolon could be used
#156: FILE: drivers/reset/sti/reset-syscfg.c:156:
+ rc->rst.ops = _reset_ops,
+ rc->rst.of_node = dev->of_node;
Signed-off-by: Philipp Zabel
---
drivers/reset/sti/reset-syscfg.c | 2 +
should use tabs where possible
#87: FILE: drivers/reset/reset-zynqmp.c:87:
+.num_resets = VERSAL_NR_RESETS,$
WARNING: please, no spaces at the start of a line
#87: FILE: drivers/reset/reset-zynqmp.c:87:
+.num_resets = VERSAL_NR_RESETS,$
Signed-off-by: Philipp Zabel
Fixes a checkpatch warning:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
#55: FILE: drivers/reset/reset-berlin.c:55:
+ unsigned offset, bit;
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-berlin.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
,
+ const char *id, int index, bool shared,
CHECK: Alignment should match open parenthesis
#781: FILE: drivers/reset/core.c:781:
+struct reset_control *__devm_reset_control_get(struct device *dev,
+ const char *id, int index, bool shared,
Signed-off-by: Philipp
On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote:
[...]
> +static int fu740_pcie_probe(struct platform_device *pdev)
> +{
[...]
> + /* Fetch reset */
> + afp->rst = devm_reset_control_get(dev, NULL);
Please use
afp->rst = devm_reset_control_get_exclusive(dev, NULL);
e = pd->va + PRCI_DEVICESRESETREG_OFFSET;
> + spin_lock_init(>reset.lock);
> +
> + r = devm_reset_controller_register(>dev, >reset.rcdev);
> + if (r) {
> + dev_err(dev, "could not register reset controller: %d\n", r);
> + return r;
> + }
> r = __prci_register_clocks(dev, pd, desc);
> +
Accidental whitespace?
Otherwise,
Reviewed-by: Philipp Zabel
regards
Philipp
onfigurations has been initialized, instead of de-asserting
> in probe. Fix it here.
>
> Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
> Signed-off-by: Kishon Vijay Abraham I
> Cc: # v5.4+
Reviewed-by: Philipp Zabel
regards
Philipp
set_control_get_optional(dev, "sierra_apb");
> + rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
> if (IS_ERR(rst)) {
> dev_err(dev, "failed to get apb reset\n");
> return PTR_ERR(rst);
Oh, nevermind my comment on the previous patch.
Reviewed-by: Philipp Zabel
regards
Philipp
(dev, "failed to get reset\n");
> + return PTR_ERR(rst);
> + }
> + sp->phy_rst = rst;
> +
> + rst = devm_reset_control_get_optional(dev, "sierra_apb");
... and
rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
here (no functional change).
With that,
Reviewed-by: Philipp Zabel
regards
Philipp
Fernández Rojas
> ---
> v5: remove reset_control_rearm().
Reviewed-by: Philipp Zabel
regards
Philipp
On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote:
> Le 03/03/2021 à 15:17, Philipp Zabel a écrit :
> > Hi Benjamin,
> >
> > On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> > > The two VPUs inside IMX8MQ share the same control block whi
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> IMX8MQ SoC got a dedicated hardware block to reset the video processor
> units (G1 and G2).
>
> Signed-off-by: Benjamin Gaignard
> ---
> drivers/reset/Kconfig| 8 ++
> drivers/reset/Makefile | 1 +
>
On Tue, 2021-02-02 at 22:15 +, Cristian Marussi wrote:
> Port driver to the new SCMI Reset interface based on protocol handles
> and common devm_get_ops().
>
> Cc: Philipp Zabel
> Signed-off-by: Cristian Marussi
Acked-by: Philipp Zabel
regards
Philipp
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> Rather use a reset like feature inside the driver use the reset
> controller API to get the same result.
>
> Signed-off-by: Benjamin Gaignard
> ---
> drivers/staging/media/hantro/Kconfig| 1 +
>
Hi Benjamin,
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> The two VPUs inside IMX8MQ share the same control block which can be see
> as a reset hardware block.
This isn't a reset controller though. The control block also contains
clock gates of some sort and a filter register
Hi Álvaro,
On Wed, 2021-02-24 at 09:22 +0100, Álvaro Fernández Rojas wrote:
[...]
> @@ -115,6 +121,8 @@ static void bcm2835_rng_cleanup(struct hwrng *rng)
> /* disable rng hardware */
> rng_writel(priv, 0, RNG_CTRL);
>
> + reset_control_rearm(priv->reset);
> +
> if
Follow the clock and regulator subsystems' lead and add a bulk API
for reset controls.
Signed-off-by: Philipp Zabel
---
drivers/reset/core.c | 213 +
include/linux/reset.h | 238 ++
2 files changed, 451 insertions
Hi Dmitry,
On Wed, 2021-03-03 at 11:28 +0300, Dmitry Osipenko wrote:
> 02.03.2021 14:21, Dmitry Osipenko пишет:
> > The I2S reset may be asserted at a boot time. Tegra30 I2S driver doesn't
> > manage the reset control and currently it happens to work because reset
> > is implicitly deasserted by
Hi Sven,
On Wed, Feb 10, 2021 at 01:29:29PM -0500, Sven Van Asbroeck wrote:
> Found it!
>
> The i.MX6QuadPlus has two pairs of PREs, which use the extended
> section of the iRAM. The Classic does not have any PREs or extended
> iRAM:
>
> pre1: pre@21c8000 {
>compatible = "fsl,imx6qp-pre";
>
Hi Dmitry,
On Sat, 2021-01-23 at 19:34 +0300, Dmitry Osipenko wrote:
> NVIDIA Tegra DRM and media drivers will need a resource-managed-optional
> variant of reset_control_get_exclusive_released() in order to switch away
> from a legacy Tegra-specific PD API to a GENPD API without much hassle.
>
The bcm6345_reset_ops structure is never modified. Make it const.
Signed-off-by: Philipp Zabel
---
drivers/reset/reset-bcm6345.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c
index 737e4e81f6b7..ac6c7ad1deda
Hi Steen,
On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote:
> Signed-off-by: Steen Hegelund
> ---
> .../bindings/reset/microchip,rst.yaml | 52 +++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
Hi Steen,
thank you for the patch. In addition to Andrew's comments, I have a few
more below:
On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote:
> Signed-off-by: Steen Hegelund
> ---
> drivers/reset/Kconfig | 8 ++
> drivers/reset/Makefile | 1 +
>
Hi Mauro,
On Thu, 2021-01-14 at 09:04 +0100, Mauro Carvalho Chehab wrote:
> A function has a different name between their prototype
> and its kernel-doc markup:
>
> ../drivers/reset/core.c:888: warning: expecting prototype for
> device_reset(). Prototype was for __device_reset() instead
>
ight should be > 64: %dx%d\n",
> - sof.width, sof.height);
> + header.frame.width, header.frame.height);
> return -EINVAL;
> }
> - if (sof.components_no > MXC_JPEG_MAX_COMPONENTS) {
> + if (header.frame.num_components > V4L2_JPEG_MAX_COMPONENTS) {
> dev_err(dev, "JPEG number of components should be <=%d",
> - MXC_JPEG_MAX_COMPONENTS);
> + V4L2_JPEG_MAX_COMPONENTS);
> return -EINVAL;
> }
> /* check and, if necessary, patch component IDs*/
> + psof = (struct mxc_jpeg_sof *)header.sof.start;
> + psos = (struct mxc_jpeg_sos *)header.sos.start;
> if (!mxc_jpeg_valid_comp_id(dev, psof, psos))
> dev_warn(dev, "JPEG component ids should be 0-3 or 1-4");
>
> - img_fmt = mxc_jpeg_get_image_format(dev, );
> - if (img_fmt == MXC_JPEG_INVALID)
> + fourcc = mxc_jpeg_get_image_format(dev, header);
> + if (fourcc == 0)
> return -EINVAL;
>
> /*
> @@ -1413,12 +1282,11 @@ static int mxc_jpeg_parse(struct mxc_jpeg_ctx *ctx,
>* encoded with 3 components have RGB colorspace, see Recommendation
>* ITU-T T.872 chapter 6.5.3 APP14 marker segment for colour encoding
>*/
> - if (img_fmt == MXC_JPEG_YUV444 && app14 && app14_transform == 0)
> - img_fmt = MXC_JPEG_RGB;
> -
> - if (mxc_jpeg_imgfmt_to_fourcc(img_fmt, )) {
> - dev_err(dev, "Fourcc not found for %d", img_fmt);
> - return -EINVAL;
> + if (fourcc == V4L2_PIX_FMT_YUV24 || fourcc == V4L2_PIX_FMT_RGB24) {
> + if (header.app14_tf == V4L2_JPEG_APP14_TF_CMYK_RGB)
> + fourcc = V4L2_PIX_FMT_RGB24;
> + else
> + fourcc = V4L2_PIX_FMT_YUV24;
> }
See above, this fixup could be moved into mxc_jpeg_get_image_format().
With that,
Reviewed-by: Philipp Zabel
regards
Philipp
+ *tf = ret;
> +
> + skip = lp - 2 - 11;
> + ret = jpeg_skip(stream, skip);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
This could be simplified to
return jpeg_skip(stream, skip);
although it would be better style to move the *tf = ... assignment down
past the last error return instead. Either way,
Reviewed-by: Philipp Zabel
regards
Philipp
On Fri, 2021-01-08 at 10:03 +0100, Daniel Vetter wrote:
> On Fri, Jan 8, 2021 at 9:55 AM Randy Dunlap wrote:
> > On 1/6/21 7:01 PM, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > Changes since 20210106:
> > >
> >
> > on x86_64:
> >
> > ld: drivers/gpu/drm/imx/parallel-display.o: in
DEFAULT;
> fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
> fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
Thank you,
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Paul,
On Thu, 2021-01-07 at 14:40 +0100, Paul Kocialkowski wrote:
> The Rockchip PX30 SoC has a Hantro VPU that features a decoder (VDPU2)
> and an encoder (VEPU2). It is similar to the RK3399's VPU but takes an
> extra clock (SCLK).
>
> Signed-off-by: Paul Kocialkowski
> ---
>
Hi Zheng,
On Wed, 2021-01-06 at 21:18 +0800, Zheng Yongjun wrote:
> Use resource_size rather than a verbose computation on
> the end and start fields.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/staging/media/hantro/hantro_v4l2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
break;
> + }
> ret = jpeg_parse_quantization_tables(,
> out->frame.precision,
> out->quantization_tables);
Reviewed-by: Philipp Zabel
regards
Philipp
F_UNKNOWN for the
uninitialized / error state.
> /* loop through marker segments */
> while ((marker = jpeg_next_marker()) >= 0) {
> switch (marker) {
> @@ -519,7 +556,9 @@ int v4l2_jpeg_parse_header(void *buf, size_t len, struct
> v4l2_jpeg_header *out)
> ret = jpeg_parse_restart_interval(,
> >restart_interval);
> break;
> -
> + case APP14:
> + out->app14_tf = jpeg_parse_app14_data();
Same as above in case of -EINVAL return. Apart from this,
Reviewed-by: Philipp Zabel
regards
Philipp
fd->release= video_device_release_empty;
> vfd->lock = >dev_mutex;
> vfd->v4l2_dev = >v4l2_dev;
> vfd->vfl_dir= VFL_DIR_M2M;
Thank you,
Reviewed-by: Philipp Zabel
regards
Philipp
On Fri, 2020-12-11 at 16:58 +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/gpu/drm/imx/parallel-display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Tue, 2020-12-08 at 20:46 +0800, Zhen Lei wrote:
> v2 --> v3:
> 1. Keep device tree patches and reset driver patch separate, as they were in
> v1.
>That is, revert v2.
> 2. When the new compatible match failed, fall back to the deprecated
> compatible.
> 3. Fix a typo, correct
On Fri, 2020-11-27 at 12:14 +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> BCM4908 was built using older PCIe hardware block that requires using
> external reset block controlling PERST# signals.
>
> Signed-off-by: Rafał Miłecki
Thank you, both applied to reset/next.
regards
Philipp
Hi Zhen,
On Fri, 2020-12-04 at 09:42 +0800, Zhen Lei wrote:
> The vendor prefix of "Hisilicon Limited" is "hisilicon", it is clearly
> stated in "vendor-prefixes.yaml".
>
> Fixes: 1527058736fa ("reset: hisilicon: add reset-hi3660")
> Fixes: 35ca8168133c ("arm64: dts: Add dts files for Hisilicon
gt; + fmt->colorspace = V4L2_COLORSPACE_JPEG;
> fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
> fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
> fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
Thank you,
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Rafał,
On Fri, 2020-12-04 at 10:37 +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
> has to be handled in the proper order.
>
> One unusual thing about this controller is that is provides access to
> the MDIO bus.
On Fri, 2020-12-04 at 14:13 +, Mirela Rabulea (OSS) wrote:
> Hi Phipipp,
>
> On Wed, 2020-12-02 at 16:18 +0100, Philipp Zabel wrote:
> > Hi Mirela,
> >
> > On Thu, 2020-11-12 at 05:05 +0200, Mirela Rabulea (OSS) wrote:
> > > From: Mirela Rabulea
> >
On Fri, 2020-12-04 at 17:38 +0800, Zhen Lei wrote:
> When I do dt_binding_check for any YAML file, below wanring is always
> reported:
>
> xxx/media/coda.yaml: 'additionalProperties' is a required property
> xxx/media/coda.yaml: ignoring, error in schema:
> warning: no schema found in file:
On Thu, 2020-12-03 at 20:02 +0800, Zhen Lei wrote:
> The vendor prefix of "Hisilicon Limited" is "hisilicon", it is clearly
> stated in "vendor-prefixes.yaml".
>
> Fixes: 1527058736fa ("reset: hisilicon: add reset-hi3660")
> Signed-off-by: Zhen Lei
> Cc: Zhangfei Gao
> ---
>
On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote:
> Force the write operation in case the read already happens
> to return the correct value.
>
> Signed-off-by: Crystal Guo
> ---
> drivers/reset/reset-ti-syscon.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
Hi,
On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote:
> Add a YAML documentation for Mediatek, which uses ti reset-controller
> driver directly. The TI reset controller provides a common reset
> management, and is suitable for Mediatek SoCs.
>
> Signed-off-by: Crystal Guo
> ---
>
On Wed, 2020-12-02 at 11:13 -0300, Fabio Estevam wrote:
> Since 5.10-rc1 i.MX is a devicetree-only platform, so simplify the code
> by removing the unused non-DT support.
>
> Signed-off-by: Fabio Estevam
Thank you, this looks fine to me now.
Reviewed-by: Philipp Zabel
regards
Philipp
On Thu, 2020-11-12 at 05:05 +0200, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea
>
> Use v4l2_jpeg_parse_header in mxc_jpeg_parse, remove the old
> parsing way, which was duplicated in other jpeg drivers.
>
> Signed-off-by: Mirela Rabulea
> ---
> Changes in v5:
> This was patch 11 in
On Wed, 2020-12-02 at 13:12 +0100, Hans Verkuil wrote:
> On 12/11/2020 04:05, Mirela Rabulea (OSS) wrote:
> > From: Mirela Rabulea
> >
> > These are optional in struct v4l2_jpeg_header, so do not parse if
> > not requested, save some time.
> >
> > Signed-off-by: Mirela Rabulea
> > ---
> >
Hi Mirela,
On Thu, 2020-11-12 at 05:05 +0200, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea
>
> These are optional in struct v4l2_jpeg_header, so do not parse if
> not requested, save some time.
>
> Signed-off-by: Mirela Rabulea
> ---
> drivers/media/v4l2-core/v4l2-jpeg.c | 6 ++
>
/* the first bytes must be SOI, B.2.1 High-level syntax */
> + if (jpeg_get_word_be() != SOI)
> return -EINVAL;
>
> /* init value to signal if this marker is not present */
Yes, shorter, potentially faster code, and it adheres to the
specification more strictly.
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Mirela,
On Thu, 2020-11-12 at 05:05 +0200, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea
>
> According to Rec. ITU-T T.872 (06/2012) 6.5.3
> APP14 segment is for color encoding, it contains a transform flag, which
> may have values of 0, 1 and 2 and are interpreted as follows:
> 0 -
Add initial reset controller API documentation. This is mostly intended
to describe the concepts to users of the consumer API, and to tie the
kerneldoc comments we already have into the driver API documentation.
Signed-off-by: Philipp Zabel
Reviewed-by: Randy Dunlap
Reviewed-by: Amjad Ouled
On Mon, 2020-11-09 at 13:21 -0600, Dinh Nguyen wrote:
> In case of an error, call release_mem_region when an error happens
> during allocation of resources. Also add error handling for the case
> that reset_controller_register fails.
>
> Reported-by: kernel test robot
> Reported-by: Dan
rr_disable_clk_ref;
>
> - priv->reset = devm_reset_control_array_get(dev, false, false);
> + priv->reset = devm_reset_control_array_get_exclusive(dev);
> if (IS_ERR(priv->reset))
> return PTR_ERR(priv->reset);
>
Reviewed-by: Philipp Zabel
regards
Philipp
meson_gx_pwrc_vpu_probe(struct platform_device
> *pdev)
> return PTR_ERR(regmap_hhi);
> }
>
> - rstc = devm_reset_control_array_get(>dev, false, false);
> + rstc = devm_reset_control_array_get_exclusive(>dev);
> if (IS_ERR(rstc)) {
> if (PTR_ERR(rstc) != -EPROBE_DEFER)
> dev_err(>dev, "failed to get reset lines\n");
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Krzysztof,
On Tue, 2020-11-17 at 19:24 +0100, Krzysztof Kozlowski wrote:
> The iMX DRM LVDS driver uses Common Clock Framework thus it cannot be
> built on platforms without it (e.g. compile test on MIPS with RALINK and
> SOC_RT305X):
>
> /usr/bin/mips-linux-gnu-ld:
i.c:391:1: warning: the frame size of 1064 bytes is
> larger than 1024 bytes [-Wframe-larger-than=]
>
> Cc: Philipp Zabel
> Cc: Sascha Hauer
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/ipu-v3/ipu-di.c | 4
> 1 file changed, 4 d
On Mon, 2020-11-16 at 19:14 +0100, Krzysztof Kozlowski wrote:
> The iMX DRM drivers use Common Clock Framework thus they cannot be built
> on platforms without it (e.g. compile test on MIPS with RALINK and
> SOC_RT305X):
>
> /usr/bin/mips-linux-gnu-ld: drivers/gpu/drm/imx/imx-ldb.o: in
Add initial reset controller API documentation. This is mostly intended
to describe the concepts to users of the consumer API, and to tie the
kerneldoc comments we already have into the driver API documentation.
Signed-off-by: Philipp Zabel
---
Changes since the RFC [1]:
- Replaced all :c:func
On Fri, 2020-11-13 at 16:13 +0100, Jerome Brunet wrote:
> On Fri 13 Nov 2020 at 16:04, Philipp Zabel wrote:
>
> > On Fri, 2020-11-13 at 00:00 +0100, Amjad Ouled-Ameur wrote:
> > > The current reset framework API does not allow to release what is done by
> > > reset_
by: Hulk Robot
> Signed-off-by: Zhihao Cheng
Thank you,
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Zhihao,
On Mon, 2020-11-16 at 22:10 +0800, Zhihao Cheng wrote:
> Fix to return the error code from
> devm_reset_control_get_optional_exclusive() instaed of 0
> in cqspi_probe().
>
> Fixes: 31fb632b5d43ca ("spi: Move cadence-quadspi driver to drivers/spi/")
> Reported-by: Hulk Robot
>
On Fri, 2020-11-13 at 00:00 +0100, Amjad Ouled-Ameur wrote:
> The current reset framework API does not allow to release what is done by
> reset_control_reset(), IOW decrement triggered_count. Add the new
> reset_control_rearm() call to do so.
>
> When reset_control_reset() has been called once,
On Mon, 2020-11-09 at 11:21 -0500, Jim Quinlan wrote:
> On Mon, Nov 9, 2020 at 5:05 AM Philipp Zabel wrote:
> > Hi Jim,
> >
> > On Fri, 2020-11-06 at 14:17 -0500, Jim Quinlan wrote:
> > > Before, only control_reset() was implemented. However, the reset
On Mon, 2020-11-09 at 10:46 +0100, Martin Kepplinger wrote:
> As described in NXPs' linux tree, the imx8m SoC includes the same
> CSI bridge hardware that is part of imx7d. We should be able to
> use the "fsl,imx7-csi" driver for imx8m directly.
>
> Since ipuv3 is not relevant for imx8m we create
On Mon, 2020-11-02 at 13:57 -0600, Dinh Nguyen wrote:
> In case of an error, call release_mem_region when an error happens
> during allocation of resources. Also add error handling for the case
> that reset_controller_register fails.
>
> Reported-by: kernel test robot
> Reported-by: Dan
Hi Jim,
On Fri, 2020-11-06 at 14:17 -0500, Jim Quinlan wrote:
> Before, only control_reset() was implemented. However, the reset core only
> invokes control_reset() once in its lifetime. Because we need it to invoke
> control_reset() again after resume out of S2 or S3, we have switched to
>
Hi Martin,
On Mon, 2020-11-09 at 10:13 +0100, Martin Kepplinger wrote:
> As described in NXPs' linux tree, the imx8m SoC includes the same
> CSI bridge hardware that is part of imx7d. We should be able to
> use the "fsl,imx7-csi" driver for imx8m directly.
>
> Since ipuv3 is not relevant for
On Tue, 2020-11-03 at 09:25 +0530, Kishon Vijay Abraham I wrote:
> From: Faiz Abbas
>
> Serdes lanes might be shared between multiple cores in some usecases
> and its not possible to lock PLLs for both the lanes independently
> by the two cores. This requires a bootloader to configure both the
>
On Mon, 2020-10-26 at 20:41 +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> clang warns about functions returning a 'const int' result:
>
> drivers/gpu/drm/imx/imx-tve.c:487:8: warning: type qualifiers ignored on
> function return type [-Wignored-qualifiers]
>
> Remove the extraneous
dersson
> Cc: Dave Gerlach
> Cc: Philipp Zabel
> Cc: Suman Anna
> Signed-off-by: Tony Lindgren
> ---
>
> Please review and ack if no issues. If you guys instead want to set up an
> immutable remoteproc branch with just this patch in it against v5.10-rc1
> that work
Hi Neil,
thank you for the patch.
On Mon, 2020-10-19 at 16:48 +0200, Neil Armstrong wrote:
> In order to reduce the kernel Image size on multi-platform distributions,
> make it possible to build the reset controller driver as a module.
>
> This partially reverts 8290924e ("reset: meson: make it
Hi Sameer, Rob,
On Mon, 2020-10-19 at 16:56 -0500, Rob Herring wrote:
> On Fri, Oct 16, 2020 at 08:12:55PM +0530, Sameer Pujar wrote:
> > Convert device tree bindings of graph to YAML format.
>
> Thanks for doing this.
Seconded.
> > Signed-off-by: Sameer Pujar
Hi Adrian,
On Mon, 2020-10-12 at 23:59 +0300, Adrian Ratiu wrote:
> Some SoCs might have a reset controller which disables clocks
> by default in reset state which then drivers need to unreset
> before being able to ungate a specific clock.
>
> In this specific case, the hantro driver needs to
Hi Amjad,
Thank you for the patch, comments below:
On Thu, 2020-10-01 at 15:55 +0200, Amjad Ouled-Ameur wrote:
> An update on the patch title, since we don't add an API but extend it,
> The title should rather be: Add a new call to the reset framework
I think it should even say what
> Signed-off-by: Rikard Falkeborn
Reviewed-by: Philipp Zabel
> ---
> arch/arm/mach-prima2/rstc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
> index 9d56606ac87f..1ee405e2dde9 100644
&g
ase= video_device_release_empty;
> vfd->lock = >dev_mutex;
> vfd->v4l2_dev = >v4l2_dev;
> vfd->vfl_dir= VFL_DIR_M2M;
>
>
Thank you,
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Jianjun,
On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote:
> MediaTek's PCIe host controller has three generation HWs, the new
> generation HW is an individual bridge, it supoorts Gen3 speed and
> up to 256 MSI interrupt numbers for multi-function devices.
>
> Add support for new Gen3
On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote:
> Add YAML schemas documentation for Gen3 PCIe controller on
> MediaTek SoCs.
>
> Signed-off-by: Jianjun Wang
> Acked-by: Ryder Lee
> ---
> .../bindings/pci/mediatek-pcie-gen3.yaml | 126 ++
> 1 file changed, 126
Hi Alain,
On Mon, 2020-08-31 at 22:38 +0200, Alain Volmat wrote:
> Fix formating of struct description to avoid warning highlighted
> by W=1 compilation.
>
> Fixes: e5d76075d930 ("drivers: reset: STi SoC system configuration reset
> controller support")
> Signed-off-by: Alain Volmat
Thank
On Mon, Sep 21, 2020 at 10:08:11PM +0300, Viorel Suman (OSS) wrote:
> From: Viorel Suman
>
> XCVR (Audio Transceiver) is a on-chip functional module found
> on i.MX8MP. It support HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
>
> Signed-off-by: Viorel Suman
> ---
> sound/soc/fsl/Kconfig| 10 +
>
On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote:
> SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
> which has 4 GT lanes and can used by 4 peripherals at a time.
> SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
> the GT lane for SATA controller, the
RR(pfdev->rstc));
> return PTR_ERR(pfdev->rstc);
> }
>
> - err = reset_control_deassert(pfdev->rstc);
> - if (err)
> - return err;
> -
> - return 0;
> + return reset_control_deassert(pfdev->rstc);
> }
>
> static void panfrost_reset_fini(struct panfrost_device *pfdev)
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Bernard,
On Mon, 2020-09-21 at 19:11 +0800, Bernard wrote:
> This change will speed-up a bit these ipu_idmac_get &
> ipu_idmac_put processing and there is no need to protect
> kzalloc & kfree.
I don't think that will be measurable, the channel lock is very unlikely
to be contended. It might
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