Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Mon, Jul 02, 2018 at 03:19:22PM +0300, Andy Shevchenko wrote: > On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj > wrote: > > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: > >> From: > >> > >> Adds debugfs access to registers in the

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

ters > whenever the package enters C10 and can be read from slp_s0_debug_status. > The pm states may also be latched by writing 1 to slp_s0_debug_latch > which will immediately capture the current state on the next read of > slp_s0_debug_status. Reviewed-and-tested-by: Rajneesh Bhardwaj >

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

ters > whenever the package enters C10 and can be read from slp_s0_debug_status. > The pm states may also be latched by writing 1 to slp_s0_debug_latch > which will immediately capture the current state on the next read of > slp_s0_debug_status. Reviewed-and-tested-by: Rajneesh Bhardwaj >

Re: [V3] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Fri, Jun 08, 2018 at 05:02:37PM -0700, Box, David E wrote: I am ok with the design and approach and also verified it on a Cannonlake system. I wont insist for a V4 unless Andy feels a need for respin but there are minor things that were missed. > Adds debugfs access to registers in the

Re: [V3] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Fri, Jun 08, 2018 at 05:02:37PM -0700, Box, David E wrote: I am ok with the design and approach and also verified it on a Cannonlake system. I wont insist for a V4 unless Andy feels a need for respin but there are minor things that were missed. > Adds debugfs access to registers in the

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Wed, May 30, 2018 at 03:53:12AM -0700, David E. Box wrote: Hi Dave, > Hi Rajneesh, > > On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote: > > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: > > > > Thanks for sending this, Dave. Few comm

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Wed, May 30, 2018 at 03:53:12AM -0700, David E. Box wrote: Hi Dave, > Hi Rajneesh, > > On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote: > > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: > > > > Thanks for sending this, Dave. Few comm

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: Thanks for sending this, Dave. Few comments below. > Adds debugfs access to registers in the Cannon Point PCH PMC that are Please use Cannonlake PCH. > useful for debugging #SLP_S0 signal assertion and other low power related

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: Thanks for sending this, Dave. Few comments below. > Adds debugfs access to registers in the Cannon Point PCH PMC that are Please use Cannonlake PCH. > useful for debugging #SLP_S0 signal assertion and other low power related

[tip:x86/dma] x86/i8237: Register device based on FADT legacy boot flag

Commit-ID: f79b1c573cb4dc551919f81ed5797419f6fc1f3a Gitweb: https://git.kernel.org/tip/f79b1c573cb4dc551919f81ed5797419f6fc1f3a Author: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> AuthorDate: Thu, 29 Mar 2018 20:36:55 +0530 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/dma] x86/i8237: Register device based on FADT legacy boot flag

Commit-ID: f79b1c573cb4dc551919f81ed5797419f6fc1f3a Gitweb: https://git.kernel.org/tip/f79b1c573cb4dc551919f81ed5797419f6fc1f3a Author: Rajneesh Bhardwaj AuthorDate: Thu, 29 Mar 2018 20:36:55 +0530 Committer: Thomas Gleixner CommitDate: Fri, 27 Apr 2018 16:44:29 +0200 x86/i8237

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Mon, Mar 26, 2018 at 03:34:44AM -0700, h...@zytor.com wrote: > On March 26, 2018 2:11:51 AM PDT, Thomas Gleixner <t...@linutronix.de> wrote: > >On Mon, 26 Mar 2018, Rajneesh Bhardwaj wrote: > > > >> On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wro

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Mon, Mar 26, 2018 at 03:34:44AM -0700, h...@zytor.com wrote: > On March 26, 2018 2:11:51 AM PDT, Thomas Gleixner wrote: > >On Mon, 26 Mar 2018, Rajneesh Bhardwaj wrote: > > > >> On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wrote: > >> > On Th

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wrote: > On Thu, 22 Mar 2018, Anshuman Gupta wrote: > > > From: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> > > > > >From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does > >

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wrote: > On Thu, 22 Mar 2018, Anshuman Gupta wrote: > > > From: Rajneesh Bhardwaj > > > > >From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does > > not support legacy DMA operations

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Thu, Mar 22, 2018 at 03:51:58PM +0530, Anshuman Gupta wrote: Adding Thomas. > From: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> > > From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does > not support legacy DMA operations to IO ports 81h-83h,

Re: [PATCH v3] x86: i8237: Register based on FADT legacy boot flag

On Thu, Mar 22, 2018 at 03:51:58PM +0530, Anshuman Gupta wrote: Adding Thomas. > From: Rajneesh Bhardwaj > > From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does > not support legacy DMA operations to IO ports 81h-83h, 87h, 89h-8Bh, 8Fh. > Currently this d

Re: [PATCH] ACPI: Add Time and Alarm Device (TAD) driver

On Fri, Mar 16, 2018 at 01:51:01PM +0100, Rafael J. Wysocki wrote: > From: Rafael J. Wysocki > > Introduce a driver for the ACPI Time and Alarm Device (TAD) based on > Section 9.18 of ACPI 6.2. Does UEFI bios for CNL support it already? Perhaps we can try this out

Re: [PATCH] ACPI: Add Time and Alarm Device (TAD) driver

On Fri, Mar 16, 2018 at 01:51:01PM +0100, Rafael J. Wysocki wrote: > From: Rafael J. Wysocki > > Introduce a driver for the ACPI Time and Alarm Device (TAD) based on > Section 9.18 of ACPI 6.2. Does UEFI bios for CNL support it already? Perhaps we can try this out and share some feedback. Some

[PATCH v2] x86: i8237: Register based on FADT legacy boot flag

@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- Changes in v2: * changed to dma_inb() This depends on recently introduced dmi_get_bios_year() helper. https://patchwork.kernel.org/patch/10252151/ arch/x86/kernel/i8237.c | 25 + 1

[PATCH v2] x86: i8237: Register based on FADT legacy boot flag

orm Controller Hub Family: BIOS Specification. https://www.intel.in/content/www/in/en/embedded/products/skylake/u-mobile/software-and-drivers.html Cc: Alan Cox Reviewed-by: Andy Shevchenko Signed-off-by: Anshuman Gupta Signed-off-by: Rajneesh Bhardwaj --- Changes in v2: * changed to dma_

[PATCH] x86: i8237: Register based on FADT legacy boot flag

el.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- This depends on recently introduced dmi_get_bios_year() helper. https://patchwork.kernel.org/patch/10252151/ arch/x86/kernel/i8237.c | 25 + 1 file changed, 25 insertions(+) diff --git a/arc

[PATCH] x86: i8237: Register based on FADT legacy boot flag

orm Controller Hub Family: BIOS Specification. https://www.intel.in/content/www/in/en/embedded/products/skylake/u-mobile/software-and-drivers.html Cc: Alan Cox Cc: Andy Shevchenko Signed-off-by: Anshuman Gupta Signed-off-by: Rajneesh Bhardwaj --- This depends on recently introduced dmi_get_bios_y

[Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address()

module to read this exported interface to calculate the PMC base address. Cc: Rafael J. Wysocki <r...@rjwysocki.net> Cc: Len Brown <l...@kernel.org> Cc: linux-a...@vger.kernel.org Acked-by: Rafael J. Wysocki <raf...@kernel.org> Tested-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.c

[Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address()

to calculate the PMC base address. Cc: Rafael J. Wysocki Cc: Len Brown Cc: linux-a...@vger.kernel.org Acked-by: Rafael J. Wysocki Tested-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada --- drivers/acpi/acpi_lpit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpit.c b

[Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake

- KBL | Y | Y | - CFL | Y | N | - Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bh

[Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake

- KBL | Y | Y | - CFL | Y | N | - Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c

[Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support

This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_pmc

[Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support

This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 85 +++ drivers/platform/x86/intel_pmc_core.h | 11 + 2

[Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT

From: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> Signed-off-by: Sriniva

[Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family

homas Gleixner <t...@linutronix.de> Suggested-by: Tony Luck <tony.l...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- arch/x86/include/asm/intel-family.h | 6 ++ 1 file changed, 6 insertio

[Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT

From: Srinivas Pandruvada Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada --- drivers/platform/x86/intel_pmc_core.c | 9 - 1 file changed

[Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family

Add CPUID of Cannonlake (CNL) processors to Intel family list. Cc: Dave Hansen Cc: Thomas Gleixner cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x...@kernel.org Reviewed-by: Thomas Gleixner Suggested-by: Tony Luck Signed-off-by: Megha Dey Signed-off-by: Rajneesh Bhardwaj --- arch/x

[Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support

. Wysocki <r...@rjwysocki.net> Cc: Len Brown <l...@kernel.org> Cc: Thomas Gleixner <t...@linutronix.de> Cc: linux-a...@vger.kernel.org Cc: x...@kernel.org Rajneesh Bhardwaj (3): x86/cpu: Add Cannonlake to Intel family platform/x86: intel_pmc_core: Add CannonLake PCH supp

[Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support

. Wysocki Cc: Len Brown Cc: Thomas Gleixner Cc: linux-a...@vger.kernel.org Cc: x...@kernel.org Rajneesh Bhardwaj (3): x86/cpu: Add Cannonlake to Intel family platform/x86: intel_pmc_core: Add CannonLake PCH support platform/x86: intel_pmc_core: Special case for Coffeelake Srinivas

Re: [Patch v1 6/8] x86/cpu: Add Cannonlake to Intel family

On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote: > On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj > <rajneesh.bhard...@intel.com> wrote: > > Add CPUID of Cannonlake (CNL) processors to Intel family list. > > > > Cc: Dave Hansen <dave.han..

Re: [Patch v1 6/8] x86/cpu: Add Cannonlake to Intel family

On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote: > On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj > wrote: > > Add CPUID of Cannonlake (CNL) processors to Intel family list. > > > > Cc: Dave Hansen > > Cc: Thomas Gleixner > > cc:

[PATCH] platform/x86: intel_pmc_core: Remove unused header file

-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- arch/x86/include/asm/pmc_core.h | 27 --- drivers/platform/x86/intel_pmc_core.c | 1 - 2 files changed, 28 deletions(-) delete mode 100644 arch/x86/include/asm/pmc_core.h diff --git a/arch/x86/include/asm/pmc_co

[PATCH] platform/x86: intel_pmc_core: Remove unused header file

-by: Rajneesh Bhardwaj --- arch/x86/include/asm/pmc_core.h | 27 --- drivers/platform/x86/intel_pmc_core.c | 1 - 2 files changed, 28 deletions(-) delete mode 100644 arch/x86/include/asm/pmc_core.h diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x86/include/asm

[Patch v1 7/8] platform/x86: intel_pmc_core: Add CannonLake PCH support

This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_pmc

[Patch v1 8/8] platform/x86: intel_pmc_core: Special case for Coffeelake

- KBL | Y | Y | - CFL | Y | N | - Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bh

[Patch v1 7/8] platform/x86: intel_pmc_core: Add CannonLake PCH support

This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 85 +++ drivers/platform/x86/intel_pmc_core.h | 11 + 2

[Patch v1 8/8] platform/x86: intel_pmc_core: Special case for Coffeelake

- KBL | Y | Y | - CFL | Y | N | - Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c

[Patch v1 6/8] x86/cpu: Add Cannonlake to Intel family

Luck <tony.l...@intel.com> Signed-off-by: Megha Dey <megha....@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- arch/x86/include/asm/intel-family.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/intel-f

[Patch v1 6/8] x86/cpu: Add Cannonlake to Intel family

Add CPUID of Cannonlake (CNL) processors to Intel family list. Cc: Dave Hansen Cc: Thomas Gleixner cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x...@kernel.org Suggested-by: Tony Luck Signed-off-by: Megha Dey Signed-off-by: Rajneesh Bhardwaj --- arch/x86/include/asm/intel-fa

[Patch v1 5/8] platform/x86: intel_pmc_core: Convert to ICPU macro

Use ICPU macro to refactor code related to x86_cpu_id for better readability. Suggested-by: Andriy Shevchenko <andriy.shevche...@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.co

[Patch v1 5/8] platform/x86: intel_pmc_core: Convert to ICPU macro

Use ICPU macro to refactor code related to x86_cpu_id for better readability. Suggested-by: Andriy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions

[Patch v1 1/8] platform/x86: intel_pmc_core: Refactor debugfs entries

these entries. Suggested-by: Andriy Shevchenko <andriy.shevche...@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_pmc_core.c | 44 +

[Patch v1 0/8] platform/x86: intel_pmc_core: Add CFL/CNL Support

> cc: Ingo Molnar <mi...@redhat.com> Cc: "H. Peter Anvin" <h...@zytor.com> Cc: x...@kernel.org Tested on Coffeelake, Cannonlake and Kabylake with 4.15-rc8 kernel. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Refactor debugfs entries platform/x86: intel_pmc_core: C

[Patch v1 1/8] platform/x86: intel_pmc_core: Refactor debugfs entries

these entries. Suggested-by: Andriy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 44 +-- 1 file changed, 16 insertions(+), 28 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b

[Patch v1 0/8] platform/x86: intel_pmc_core: Add CFL/CNL Support

d Kabylake with 4.15-rc8 kernel. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Refactor debugfs entries platform/x86: intel_pmc_core: Convert to ICPU macro x86/cpu: Add Cannonlake to Intel family platform/x86: intel_pmc_core: Add CannonLake PCH support platform/x86: intel_pmc_core: Sp

[Patch v1 2/8] platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration

upport. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> --- drivers/platform/x86/intel_pmc_core.c | 91 --- drivers/platform/x86/intel_pmc_core.h | 3 +- 2 files chan

[Patch v1 2/8] platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration

standard methods like ACPI LPIT which can also be used for obtaining this value. For simplicity, this value can be hardcoded as it won't change. Since we don't have a PMC PCI device on any platform after Kabylake, this creates a foundation for future SoC support. Signed-off-by: Rajneesh Bhardwaj

[Patch v1 4/8] platform/x86: intel_pmc_core: Read base address from LPIT

From: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> Signed-off-by: Sriniva

[Patch v1 4/8] platform/x86: intel_pmc_core: Read base address from LPIT

From: Srinivas Pandruvada Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada --- drivers/platform/x86/intel_pmc_core.c | 9 - 1 file changed

[Patch v1 3/8] ACPI / LPIT: Export lpit_read_residency_count_address()

module to read this exported interface to calculate the PMC base address. Cc: Rafael J. Wysocki <r...@rjwysocki.net> Cc: Len Brown <l...@kernel.org> Cc: linux-a...@vger.kernel.org Tested-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas

[Patch v1 3/8] ACPI / LPIT: Export lpit_read_residency_count_address()

to calculate the PMC base address. Cc: Rafael J. Wysocki Cc: Len Brown Cc: linux-a...@vger.kernel.org Tested-by: Rajneesh Bhardwaj Signed-off-by: Srinivas Pandruvada --- drivers/acpi/acpi_lpit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c

[PATCH v1 0/6] platform/x86: intel_pmc_core: PMC Driver cleanup

This patch series aims to cleanup the PMC Core driver and convert it to a module. Subsequent patch series will add support for newer Intel SoC like Coffeelake and Cannonlake, this series builds a foundation for them. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Remove unused EXPORTED

[PATCH v1 0/6] platform/x86: intel_pmc_core: PMC Driver cleanup

This patch series aims to cleanup the PMC Core driver and convert it to a module. Subsequent patch series will add support for newer Intel SoC like Coffeelake and Cannonlake, this series builds a foundation for them. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Remove unused EXPORTED

[PATCH v1 3/6] platform/x86: intel_pmc_core: Fix kernel doc for pmc_dev

Fix invalid field information and add missing fields in kernel doc comments. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_pmc_core.h | 12 +++- 1 fil

[PATCH v1 3/6] platform/x86: intel_pmc_core: Fix kernel doc for pmc_dev

Fix invalid field information and add missing fields in kernel doc comments. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.h | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/platform/x86

[PATCH v1 4/6] platform/x86: intel_pmc_core: Change driver to a module

From: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Allow the driver to be a module since builtin_pci_driver funtionality is no longer needed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bha

[PATCH v1 4/6] platform/x86: intel_pmc_core: Change driver to a module

From: Srinivas Pandruvada Allow the driver to be a module since builtin_pci_driver funtionality is no longer needed. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/Kconfig | 2 +- drivers/platform/x86/intel_pmc_core.c | 15

[PATCH v1 5/6] platform/x86: intel_pmc_core: Fix file permission warnings

Symbolic permissions 'S_IRUGO' are not preferred. This patch changes the debugfs files to use octal permissions '0644' or '0444' as needed by the attribute. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@

[PATCH v1 5/6] platform/x86: intel_pmc_core: Fix file permission warnings

Symbolic permissions 'S_IRUGO' are not preferred. This patch changes the debugfs files to use octal permissions '0644' or '0444' as needed by the attribute. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 18 +++--- 1

[PATCH v1 2/6] platform/x86: intel_pmc_core: Remove unused variable

base_address field is redundant and unused in the driver so get rid of it. Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_pmc_core.h | 2 -- 1 file changed,

[PATCH v1 2/6] platform/x86: intel_pmc_core: Remove unused variable

base_address field is redundant and unused in the driver so get rid of it. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers

[PATCH v1 6/6] platform/x86: intel_pmc_core: Update Kconfig

This adds list of supported features by this driver to the Kconfig. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/Kconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/K

[PATCH v1 6/6] platform/x86: intel_pmc_core: Update Kconfig

This adds list of supported features by this driver to the Kconfig. Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/Kconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 683a875f3b6c

[PATCH v1 1/6] platform/x86: intel_pmc_core: Remove unused EXPORTED API

gt; Cc: Rajat Jain <raja...@google.com> Link: https://patchwork.kernel.org/patch/9831229/ Suggested-by: Andriy Shevchenko <andriy.shevche...@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard

[PATCH v1 1/6] platform/x86: intel_pmc_core: Remove unused EXPORTED API

://patchwork.kernel.org/patch/9831229/ Suggested-by: Andriy Shevchenko Signed-off-by: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 32 drivers/platform/x86/intel_pmc_core.h | 1 - 2 files changed, 33 deletions

[PATCH v1 0/6] PMC Driver cleanup

This patch series aims to cleanup the PMC Core driver and convert it to a module. Subsequent patch series will add support for newer Intel SoC like Coffeelake and Cannonlake, this series builds a foundation for them. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Remove unused EXPORTED

[PATCH v1 0/6] PMC Driver cleanup

This patch series aims to cleanup the PMC Core driver and convert it to a module. Subsequent patch series will add support for newer Intel SoC like Coffeelake and Cannonlake, this series builds a foundation for them. Rajneesh Bhardwaj (5): platform/x86: intel_pmc_core: Remove unused EXPORTED

[PATCH 1/3] platform/x86: intel_telemetry: Fix load failure info

Intel Telemetry driver depends on IPC1 interface. If IPC1 interface is disabled on a given platform by the system firmware, the driver does not load but prints misleading information in the dmesg logs. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platfo

[PATCH 1/3] platform/x86: intel_telemetry: Fix load failure info

Intel Telemetry driver depends on IPC1 interface. If IPC1 interface is disabled on a given platform by the system firmware, the driver does not load but prints misleading information in the dmesg logs. Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_telemetry_pltdrv.c | 1 - 1

[PATCH 2/3] platform/x86: intel_telemetry: Fix typos

Telemetry word is misspelled several times in this file as Telemtry. This fixes the spelling mistake and folds in another minor typo. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_telemetry_pltdrv.c | 14 +++--- 1 file changed, 7 inse

[PATCH 2/3] platform/x86: intel_telemetry: Fix typos

Telemetry word is misspelled several times in this file as Telemtry. This fixes the spelling mistake and folds in another minor typo. Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_telemetry_pltdrv.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff

[PATCH 3/3] platform/x86: intel_telemetry: cleanup redundant headers

Removes unnecessary header files included in the driver and sorts the remaining ones in the alphabetical order. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_telemetry_core.c| 3 +-- drivers/platform/x86/intel_telemetry_debugfs

[PATCH 3/3] platform/x86: intel_telemetry: cleanup redundant headers

Removes unnecessary header files included in the driver and sorts the remaining ones in the alphabetical order. Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_telemetry_core.c| 3 +-- drivers/platform/x86/intel_telemetry_debugfs.c | 8 +++- drivers/platform/x86

Re: your mail

On Fri, Aug 18, 2017 at 11:12:14PM +0530, Rajneesh Bhardwaj wrote: > Bcc: > Subject: Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states > residency info > Reply-To: > In-Reply-To: > <cahp75vd5wnio-rcebentonywojf2+88fdvqkuv1hzv3cdca...@mail.gmail.com> >

Re: your mail

On Fri, Aug 18, 2017 at 11:12:14PM +0530, Rajneesh Bhardwaj wrote: > Bcc: > Subject: Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states > residency info > Reply-To: > In-Reply-To: > > Please ignore my previous email without subject. It was sent by mistake. &

Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

On Fri, Aug 18, 2017 at 08:17:32PM +0300, Andy Shevchenko wrote: > +PeterZ (since I mentioned his name) > > On Fri, Aug 18, 2017 at 5:58 PM, Rajneesh Bhardwaj > <rajneesh.bhard...@intel.com> wrote: > > On Fri, Aug 18, 2017 at 03:57:34PM +0300, Andy Shevchenko wrote: > &

Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

On Fri, Aug 18, 2017 at 08:17:32PM +0300, Andy Shevchenko wrote: > +PeterZ (since I mentioned his name) > > On Fri, Aug 18, 2017 at 5:58 PM, Rajneesh Bhardwaj > wrote: > > On Fri, Aug 18, 2017 at 03:57:34PM +0300, Andy Shevchenko wrote: > >> On Fri, Aug 18, 2017 at

[no subject]

his name) > > On Fri, Aug 18, 2017 at 5:58 PM, Rajneesh Bhardwaj > <rajneesh.bhard...@intel.com> wrote: > > On Fri, Aug 18, 2017 at 03:57:34PM +0300, Andy Shevchenko wrote: > >> On Fri, Aug 18, 2017 at 3:37 PM, Rajneesh Bhardwaj > >> <rajneesh.bhard...@intel.com

[no subject]

Bcc: Subject: Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info Reply-To: In-Reply-To: On Fri, Aug 18, 2017 at 08:17:32PM +0300, Andy Shevchenko wrote: > +PeterZ (since I mentioned his name) > > On Fri, Aug 18, 2017 at 5:58 PM, Rajneesh Bhardwaj

Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

On Fri, Aug 18, 2017 at 03:57:34PM +0300, Andy Shevchenko wrote: > On Fri, Aug 18, 2017 at 3:37 PM, Rajneesh Bhardwaj > <rajneesh.bhard...@intel.com> wrote: > > This patch introduces a new debugfs entry to read current Package C-state > > residency values and, on

Re: [PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

On Fri, Aug 18, 2017 at 03:57:34PM +0300, Andy Shevchenko wrote: > On Fri, Aug 18, 2017 at 3:37 PM, Rajneesh Bhardwaj > wrote: > > This patch introduces a new debugfs entry to read current Package C-state > > residency values and, one new kernel API to read the Package C-10 res

[PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

state_residency Package C2 : 0xec2e21735f Package C3 : 0xc30113ba4 Package C6 : 0x9ef4be15c5 Package C7 : 0x1e011904 Package C8 : 0x3c5653cfe5a Package C9 : 0x0 Package C10 : 0x16fff4289 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- * Applie

[PATCH] platform/x86: intel_pmc_core: Add Package C-states residency info

state_residency Package C2 : 0xec2e21735f Package C3 : 0xc30113ba4 Package C6 : 0x9ef4be15c5 Package C7 : 0x1e011904 Package C8 : 0x3c5653cfe5a Package C9 : 0x0 Package C10 : 0x16fff4289 Signed-off-by: Rajneesh Bhardwaj --- * Applied on top of "Make the d

Re: [PATCH] pinctrl: intel: Disable GPIO pin interrupts in suspend

; programming the corresponding GPIO pad registers. Only IRQs that are not > > marked for wake are disabled. > > > > Signed-off-by: Rushikesh S Kadam <rushikesh.s.ka...@intel.com> > > Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com> Reviewed-and-tested-by: Rajn

Re: [PATCH] pinctrl: intel: Disable GPIO pin interrupts in suspend

IO pad registers. Only IRQs that are not > > marked for wake are disabled. > > > > Signed-off-by: Rushikesh S Kadam > > Reviewed-by: Andy Shevchenko Reviewed-and-tested-by: Rajneesh Bhardwaj > > > --- > > drivers/pinctrl/intel/pinctrl-intel.c | 1 + > >

[PATCH v2 2/2] Telemetry: remove redundant macro definition

Telemetry driver includes intel_telemetry.h which defines TELEM_MAX_OS_ALLOCATED_EVENTS already. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_telemetry_pltdrv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/platfo

[PATCH v2 1/2] platform/x86: Add GLK PSS Event Table

Some of the Primary Subsystem events differ on Gemini Lake but the IOSS events remain same. This patch adds the updated PSS event table to enable Telemetry driver on Gemini Lake. Signed-off-by: Shanth Murthy <shanth.mur...@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@

[PATCH v2 1/2] platform/x86: Add GLK PSS Event Table

Some of the Primary Subsystem events differ on Gemini Lake but the IOSS events remain same. This patch adds the updated PSS event table to enable Telemetry driver on Gemini Lake. Signed-off-by: Shanth Murthy Signed-off-by: Rajneesh Bhardwaj --- Changes in v2: * Dropped "Add Audio doma

[PATCH v2 2/2] Telemetry: remove redundant macro definition

Telemetry driver includes intel_telemetry.h which defines TELEM_MAX_OS_ALLOCATED_EVENTS already. Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_telemetry_pltdrv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/platform/x86/intel_telemetry_pltdrv.c b/drivers

Re: [PATCH 3/3] platform/x86: Add Audio domain PG status events

main PG status events > > > > From: "Murthy, Shanth" <shanth.mur...@intel.com> > > > > This patch adds events to ioss telemetry to read the power gating status for > > the audio domain. > > > > Signed-off-by: Shanth Murthy <shanth.mur...@i

Re: [PATCH 3/3] platform/x86: Add Audio domain PG status events

s patch adds events to ioss telemetry to read the power gating status for > > the audio domain. > > > > Signed-off-by: Shanth Murthy > > Signed-off-by: Rajneesh Bhardwaj > > --- > > arch/x86/include/asm/intel_telemetry.h| 2 +- > > drivers/platform

[PATCH 3/3] platform/x86: Add Audio domain PG status events

From: "Murthy, Shanth" <shanth.mur...@intel.com> This patch adds events to ioss telemetry to read the power gating status for the audio domain. Signed-off-by: Shanth Murthy <shanth.mur...@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com&g

[PATCH 3/3] platform/x86: Add Audio domain PG status events

From: "Murthy, Shanth" This patch adds events to ioss telemetry to read the power gating status for the audio domain. Signed-off-by: Shanth Murthy Signed-off-by: Rajneesh Bhardwaj --- arch/x86/include/asm/intel_telemetry.h| 2 +- drivers/platform/x86/intel_telemetry_pl

[PATCH 2/3] Telemetry: remove redundant macro definition

Telemetry driver includes intel_telemetry.h which defines TELEM_MAX_OS_ALLOCATED_EVENTS already. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhard...@intel.com> --- drivers/platform/x86/intel_telemetry_pltdrv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/platfo

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