On Thu, Jul 23, 2020 at 01:03:17PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 23, 2020 at 04:38:55AM +0300, Serge Semin wrote:
> > GPIO-lib provides a ready-to-use interface to initialize an IRQ-chip on
> > top of a GPIO chip. It's better from maintainability and readability
&g
ver Generic IRQ-chip implementation with the GPIO-lib IRQ-chip one.
Finally the DW APB GPIO device probe procedure is simplified by
converting the code to be using the device managed resources for the
reference clocks initialization, reset control assertion/de-assertion
and GPIO-chip registration.
Signed-off
all
motivate the platform developer to convert the DW APB GPIO DT-nodes to
using the standard number of GPIOs property.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwa
to be done for it. All the cleanups are now performed by means of the
device managed framework.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c | 37 ++---
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio
It's redundant to have a vendor-specific property describing a number of
GPIOS while there is a generic one. Let's mark the former one as
deprecated and define the "ngpios" property supported with constraints
of being within [1; 32] range.
Signed-off-by: Serge Semin
---
.../devicetre
that
the clocks acquisition and release will be purely managed by the device
resources interface.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio
will be purely managed by the device resources interface.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index 3f727ebe7f9a
or not.
7) Discard the acpi_gpiochip_{request,free}_interrupts()
invocations, since they will be called from
gpiochip_add_irqchip()/gpiochip_irqchip_remove() anyway.
8) Alter CONFIG_GPIO_DWAPB kernel config to select
CONFIG_GPIOLIB_IRQCHIP instead of CONFIG_GENERIC_IRQ_CHIP.
Signed-off-by: Serge
For better readability let's group all the IRQ handler in a single place
of the driver instead of having them scatter around all over the file.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio
" and
"interrupts", which will be used by the driver to correctly find the
controller memory region and handle its events. The rest of the properties
are optional, since in case if either "dma-channels" or "dma-masters" isn't
specified, the driver will attempt to auto-d
Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.
Signed-off-by: Serge Semin
Reviewed-by: Andy
will cause less dw_desc allocations, less LLP reinitializations,
better DMA device performance.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v2:
- This is a new patch created in place of the dropped one:
"dmaengine: dw: Add LLP and block size config acce
v8:
- Meld the patch
[PATCH v7 08/11] dmaengine: dw: Add dummy device_caps callback
into
[PATCH v7 10/11] dmaengine: dw: Introduce max burst length hw config
- Replace max_sg_nents with max_sg_burst capability name.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc
. The channels and
controller-specific max_burst length initialization will be introduced
by the follow-up patches.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v4:
- This is a new patch suggested by Andy.
Changelog v5:
- Introduce macro with extreme min and max burst
DMA transaction.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v3:
- This is a new patch created as a result of the discussion with Vinud and
Andy in the framework of DW DMA burst and LLP capabilities.
Changelog v4:
- Use explicit if-else statement when assigning
capability
we make sure a DMA consumer will get the channel-specific max burst
length.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v2:
- Rearrange SoBs.
- Discard dwc_get_maxburst() accessor. It's enough to have a clamping
guard against exceeding the hardware max burst
driver with 0 if there is no limitation of the number of SG entries
atomically executed and with non-zero value if there is such constraints,
so the upper limit is determined by the number set to the property.
Suggested-by: Andy Shevchenko
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
then the LLP register is hardcoded to
zero, so the blocks chaining based on the LLPs is unsupported.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v2:
- Rearrange SoBs.
- Add comment about why hardware accelerated LLP list support depends
on both MBLK_EN and HC_LLP configs
if provided it gets called from the dma_get_slave_caps() method and is
able to override the generic DMA-device capabilities.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v3:
- This is a new patch created as a result of the discussion with Vinod and
Andy in the framework
This array property is used to indicate the maximum burst transaction
length supported by each DMA channel.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
---
Changelog v2:
- Rearrange SoBs.
- Move $ref to the root level of the properties. So do
-by: Serge Semin
---
Changelog v3:
- This is a new patch.
---
drivers/tty/serial/8250/8250_dw.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index aab36789..12866083731d 100644
a functionality of the ref clock events
handler for the current UART port, since uartclk update will be done
a bit further in the generic serial8250_do_set_termios() function.
Signed-off-by: Serge Semin
---
Changelog v2:
- Move exclusive ref clock lock/unlock precudures to the 8250 port
.ru
Changelog v8:
- Add a new patch:
"serial: 8250_dw: Pass the same rate to the clk round and set rate methods"
Link:
https://lore.kernel.org/linux-serial/20200714124808.21493-1-sergey.se...@baikalelectronics.ru
Changelog v9:
- Resend
Signed-off-by: Serge Semin
Cc: Alexey Malahov
All of these things is done in a coherent
way by calling the serial8250_update_uartclk() method provided in this
patch. Though note that it isn't supposed to be called from within the
UART port callbacks because the locks using to the protect the UART port
data are already taken in there.
Signed-off-by: Se
Indeed according to the clk API if clk_round_rate() has successfully
accepted a rate, then in order setup the clock with value returned by the
clk_round_rate() the clk_set_rate() method must be called with the
original rate value.
Suggested-by: Russell King
Signed-off-by: Serge Semin
rst length calculated earlier by the
dw_spi_dma_maxburst_init() method.
Fixes: 0b2b66514fc9 ("spi: dw: Use DMA max burst to set the request thresholds")
Cc: Andy Shevchenko
Cc: Alexey Malahov
Cc: Feng Tang
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 14 +-
On Fri, Jul 17, 2020 at 06:29:49AM +0200, Daniel Lezcano wrote:
> On 14/07/2020 14:57, Serge Semin wrote:
> > Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
> > GIC timer and MIPS CPS CPUidle drivers.
> >
> > Signed-off-by: Serge Semin
On Fri, Jul 17, 2020 at 01:44:03PM +0530, Vinod Koul wrote:
> On 15-07-20, 20:08, Serge Semin wrote:
> > On Wed, Jul 15, 2020 at 04:43:15PM +0530, Vinod Koul wrote:
> > > On 10-07-20, 19:14, Serge Semin wrote:
> > > > On Fri, Jul 10, 2020 at 02:51:33
On Wed, Jul 15, 2020 at 04:43:15PM +0530, Vinod Koul wrote:
> On 10-07-20, 19:14, Serge Semin wrote:
> > On Fri, Jul 10, 2020 at 02:51:33PM +0300, Peter Ujfalusi wrote:
>
> > > Since we should be able to handle longer lists and this is kind of a
> > > hint for
> Best,
> > Daniel
> >
> > On Tue, Jul 14, 2020 at 5:41 AM Serge Semin
> > wrote:
> > >
> > > Commit 7b668c064ec3 ("serial: 8250: Fix max baud limit in generic 8250
> > > port") fixed limits of a baud rate setting for a generic 8250
On Tue, Jul 14, 2020 at 09:18:16AM -0700, Dave Jiang wrote:
>
>
> On 7/14/2020 9:08 AM, Vinod Koul wrote:
> > On 13-07-20, 13:55, Dave Jiang wrote:
> > >
> > >
> > > On 7/10/2020 2:38 AM, Serge Semin wrote:
> > > > On Fri, J
On Tue, Jul 14, 2020 at 03:28:30PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 14, 2020 at 2:58 PM Serge Semin
> wrote:
> >
> > config MIPS_CDMM
> > bool "MIPS Common Device Memory Map (CDMM) Driver"
> > - depends on CPU_MIPSR2
> &g
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
---
drivers/bus/Kconfig | 2 +-
1 file
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
GIC timer and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
Acked-by: Marc Zyngier
---
Changelog v3:
- Keep the files list alphabetically ordered.
- Add Thomas as the co-maintainer of the designated drivers
C also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge Semin
Review
linux-mips/20200602100921.1155-1-sergey.se...@baikalelectronics.ru
Changelog v4:
- Resend.
Link:
https://lore.kernel.org/linux-mips/20200617223201.23259-1-sergey.se...@baikalelectronics.ru
Changelog v5:
- Consider address and size cells being <1> by default for the DT examples.
Signed-off
platforms by default.
Signed-off-by: Serge Semin
---
Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
drivers/bus/mips_cdmm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Lowercase the example hex'es.
Changelog v5:
- Consider address and size
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
---
Changelog prev:
- Reword the changelog summary - use shorter
angelog v8:
- Add a new patch:
"serial: 8250_dw: Pass the same rate to the clk round and set rate methods"
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Thomas Bogendoerfer
Cc: Andy Shevchenko
Cc: Maxime Ripard
Cc: Will Deacon
Cc: Russell King
Cc: lin
-by: Serge Semin
---
Changelog v3:
- This is a new patch.
---
drivers/tty/serial/8250/8250_dw.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index aab36789..12866083731d 100644
a functionality of the ref clock events
handler for the current UART port, since uartclk update will be done
a bit further in the generic serial8250_do_set_termios() function.
Signed-off-by: Serge Semin
---
Changelog v2:
- Move exclusive ref clock lock/unlock precudures to the 8250 port
Indeed according to the clk API if clk_round_rate() has successfully
accepted a rate, then in order setup the clock with value returned by the
clk_round_rate() the clk_set_rate() method must be called with the
original rate value.
Suggested-by: Russell King
Signed-off-by: Serge Semin
All of these things is done in a coherent
way by calling the serial8250_update_uartclk() method provided in this
patch. Though note that it isn't supposed to be called from within the
UART port callbacks because the locks using to the protect the UART port
data are already taken in there.
Signed-off-by: Se
ot;)
Reported-by: Daniel Winkler
Signed-off-by: Serge Semin
---
Folks, sorry for a delay with the problem fix. A solution is turned out to
be a bit more complicated than I originally thought in my comment to the
Daniel revert-patch.
Please also note, that I don't have a Mediatek hardware to
Vinod Koul wrote:
> On 10-07-20, 12:38, Serge Semin wrote:
> > On Fri, Jul 10, 2020 at 11:45:03AM +0300, Andy Shevchenko wrote:
> > > On Fri, Jul 10, 2020 at 01:45:44AM +0300, Serge Semin wrote:
> > > > There are DMA devices (like ours version of Synopsys DW DMAC)
On Mon, Jul 13, 2020 at 01:22:59PM -0600, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 12:13:28PM +0200, Lars Povlsen wrote:
...
>
> > +
> > patternProperties:
> >"^.*@[0-9a-f]+$":
> > type: object
> > @@ -107,6 +122,14 @@ patternProperties:
> >spi-tx-bus-width:
> >
On Fri, Jul 10, 2020 at 02:51:33PM +0300, Peter Ujfalusi wrote:
> Hi Sergey,
>
> On 10/07/2020 12.27, Serge Semin wrote:
> > Hello Peter
> >
> > On Fri, Jul 10, 2020 at 11:31:47AM +0300, Peter Ujfalusi wrote:
> >>
> >>
> >> On 10/07/202
On Fri, Jul 10, 2020 at 11:51:23AM +0300, Andy Shevchenko wrote:
> On Fri, Jul 10, 2020 at 01:45:47AM +0300, Serge Semin wrote:
> > Since some DW DMA controllers (like one installed on Baikal-T1 SoC) may
> > have non-uniform DMA capabilities per device channels, let's add
> >
On Fri, Jul 10, 2020 at 11:45:03AM +0300, Andy Shevchenko wrote:
> On Fri, Jul 10, 2020 at 01:45:44AM +0300, Serge Semin wrote:
> > There are DMA devices (like ours version of Synopsys DW DMAC) which have
> > DMA capabilities non-uniformly redistributed between the device channel
Hello Peter
On Fri, Jul 10, 2020 at 11:31:47AM +0300, Peter Ujfalusi wrote:
>
>
> On 10/07/2020 1.45, Serge Semin wrote:
> > Some devices may lack the support of the hardware accelerated SG list
> > entries automatic walking through and execution. In this case a burd
Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.
Signed-off-by: Serge Semin
Reviewed-by: Andy
if provided it gets called from the dma_get_slave_caps() method and is
able to override the generic DMA-device capabilities.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m
capability
we make sure a DMA consumer will get the channel-specific max burst
length.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2
. The channels and
controller-specific max_burst length initialization will be introduced
by the follow-up patches.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet
will cause less dw_desc allocations, less LLP reinitializations,
better DMA device performance.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
overrides in the next commits.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the discussion with Vinud and
Andy
then the LLP register is hardcoded to
zero, so the blocks chaining based on the LLPs is unsupported.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
DMA transaction.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the discussion
This array property is used to indicate the maximum burst transaction
length supported by each DMA channel.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: linux-m
with 0 if there is no limitation for the number of SG entries
atomically executed and with non-zero value if there is such constraints,
so the upper limit is determined by the number set to the property.
Suggested-by: Andy Shevchenko
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc
aikalelectronics.ru
Changelog v7:
- Get the patches:
[PATCH v5 04/11] dmaengine: Introduce max SG list entries capability
[PATCH v5 11/11] dmaengine: dw: Initialize max_sg_nents capability
back.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc: Pavel Parkhomenko
Cc: Ramil Zaripov
" and
"interrupts", which will be used by the driver to correctly find the
controller memory region and handle its events. The rest of the properties
are optional, since in case if either "dma-channels" or "dma-masters" isn't
specified, the driver will attempt to auto-d
On Wed, Jul 01, 2020 at 02:13:36PM -0700, Daniel Winkler wrote:
>
> This change regresses the QCA6174A-3 bluetooth chip, preventing
> firmware from being properly loaded. Without this change, the
> chip works as intended.
>
> The device is the Kukui Chromebook using the Mediatek chipset
> and
Hello Daniel
On Wed, Jul 01, 2020 at 09:00:03AM +0200, Daniel Lezcano wrote:
> On 18/06/2020 00:32, Serge Semin wrote:
> > Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
> > GIC timer and MIPS CPS CPUidle drivers.
>
> Why will you add yourself in
>
> commit 7b668c064ec33f3d687c3a413d05e355172e6c92
> Author: Serge Semin
> Date: Thu May 7 02:31:32 2020 +0300
>
> serial: 8250: Fix max baud limit in generic 8250 port
>
> And you didn't cc the commit author (hereby fixed).
>
> Thanks,
>
> Lukas
Than
On Sat, Jun 20, 2020 at 01:13:56PM +0300, Andy Shevchenko wrote:
> On Sat, Jun 20, 2020 at 1:12 AM Serge Semin wrote:
> > On Thu, Jun 18, 2020 at 11:56:54AM +0300, Andy Shevchenko wrote:
> > > On Wed, Jun 17, 2020 at 01:56:48AM +0300, Serge Semin wrote:
> > > > On W
Hello Russell,
Thanks for your comments. My response is below.
On Sat, Jun 20, 2020 at 09:12:01AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 19, 2020 at 11:02:50PM +0300, Serge Semin wrote:
> > Really instead of twice checking the clk_round_rate() return value
> &
Hello Pavel
On Fri, Jun 19, 2020 at 11:07:19PM +0200, Pavel Machek wrote:
> On Fri 2020-06-19 16:32:47, Greg Kroah-Hartman wrote:
> > From: Serge Semin
> >
> > [ Upstream commit f0410bbf7d0fb80149e3b17d11d31f5b5197873e ]
> >
> > DW APB SSI DMA-part
On Thu, Jun 18, 2020 at 11:56:54AM +0300, Andy Shevchenko wrote:
> On Wed, Jun 17, 2020 at 01:56:48AM +0300, Serge Semin wrote:
> > On Wed, Jun 17, 2020 at 12:40:35AM +0300, Andy Shevchenko wrote:
> > > On Tue, Jun 16, 2020 at 11:03 PM Serge Semin
> > > wrote:
> &g
Changelog v6:
- Resend
Link:
https://lore.kernel.org/linux-serial/20200617224813.23853-1-sergey.se...@baikalelectronics.ru
Changelog v7:
- Wake the device up on the serial port divider update.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc: Pavel Parkhomenko
Cc: Alexe
All of these things is done in a coherent
way by calling the serial8250_update_uartclk() method provided in this
patch. Though note that it isn't supposed to be called from within the
UART port callbacks because the locks using to the protect the UART port
data are already taken in there.
Signed-off-by: Se
-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Maxime Ripard
Cc: Will Deacon
Cc: Russell King
Cc: linux-m...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
Changelog v3:
- This is a new patch.
---
drivers/tty/serial/8250
a functionality of the ref clock events
handler for the current UART port, since uartclk update will be done
a bit further in the generic serial8250_do_set_termios() function.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Maxime
On Thu, Jun 18, 2020 at 11:29:36AM +0300, Andy Shevchenko wrote:
> On Thu, Jun 18, 2020 at 1:50 AM Serge Semin
> wrote:
> >
> > The race condition may happen if the UART reference clock is shared with
> > some other device (on Baikal-T1 SoC it's another DW UART
On Thu, Jun 18, 2020 at 11:31:44AM +0300, Andy Shevchenko wrote:
> On Thu, Jun 18, 2020 at 11:17 AM Andy Shevchenko
> wrote:
> > On Thu, Jun 18, 2020 at 1:52 AM Serge Semin
> > wrote:
>
> > I'm wondering how this will collaborate with runtime PM.
>
> Forgot
On Thu, Jun 18, 2020 at 11:17:47AM +0300, Andy Shevchenko wrote:
> On Thu, Jun 18, 2020 at 1:52 AM Serge Semin
> wrote:
> >
> > Greg, Jiri. We've missed the last merge window. It would be pity to miss
> > the next one. Please review/merge in the series.
> >
> &
On Thu, Jun 18, 2020 at 11:21:53AM +0300, Andy Shevchenko wrote:
> On Thu, Jun 18, 2020 at 2:43 AM Serge Semin
> wrote:
> >
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with dt-schema. This commit replaces the Synopsis
>
will cause less dw_desc allocations, less LLP reinitializations,
better DMA device performance.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
. The channels and
controller-specific max_burst length initialization will be introduced
by the follow-up patches.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet
overrides in the next commits.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the discussion with Vinud and
Andy
This array property is used to indicate the maximum burst transaction
length supported by each DMA channel.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: linux-m
capability
we make sure a DMA consumer will get the channel-specific max burst
length.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2
then the LLP register is hardcoded to
zero, so the blocks chaining based on the LLPs is unsupported.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.
Signed-off-by: Serge Semin
Reviewed-by: Andy
if provided it gets called from the dma_get_slave_caps() method and is
able to override the generic DMA-device capabilities.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m
" and
"interrupts", which will be used by the driver to correctly find the
controller memory region and handle its events. The rest of the properties
are optional, since in case if either "dma-channels" or "dma-masters" isn't
specified, the driver will attempt to auto-d
ngine/20200529144054.4251-1-sergey.se...@baikalelectronics.ru
Changelog v6:
- Discard patches:
[PATCH v5 04/11] dmaengine: Introduce max SG list entries capability
[PATCH v5 11/11] dmaengine: dw: Initialize max_sg_nents capability
since for now it's not enough to have them merged in to prov
All of these things is done in a coherent
way by calling the serial8250_update_uartclk() method provided in this
patch. Though note that it isn't supposed to be called from within the
UART port callbacks because the locks using to the protect the UART port
data are already taken in there.
Signed-off-by: Se
-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Maxime Ripard
Cc: Will Deacon
Cc: Russell King
Cc: linux-m...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
Changelog v3:
- This is a new patch.
---
drivers/tty/serial/8250
a functionality of the ref clock events
handler for the current UART port, since uartclk update will be done
a bit further in the generic serial8250_do_set_termios() function.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Maxime
Changelog v6:
- Resend
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc: Pavel Parkhomenko
Cc: Alexey Kolotnikov
Cc: Ramil Zaripov
Cc: Ekaterina Skachko
Cc: Vadim Vlasov
Cc: Alexey Kolotnikov
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Maxime Ripard
Cc: Will Deaco
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
Cc: linux-m...@vger.kernel.org
---
Changelog prev:
- Lowercase the example
linux-mips/20200602100921.1155-1-sergey.se...@baikalelectronics.ru
Changelog v4:
- Resend.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Rob Herring
Cc: Arnd Bergmann
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: James Hogan
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: li
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
Cc: Alexey Malahov
Cc: linux-m
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
---
Changelog prev:
- Reword the changelog summary - use shorter
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
GIC timer and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
Acked-by: Marc Zyngier
Cc: Alexey Malahov
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- Keep the files list
C also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge Semin
Revi
platforms by default.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: devicet...@vger.kernel.org
---
Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
drivers/bus/mips_cdmm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/bus
On Wed, Jun 17, 2020 at 12:40:35AM +0300, Andy Shevchenko wrote:
> On Tue, Jun 16, 2020 at 11:03 PM Serge Semin wrote:
> > On Mon, Jun 08, 2020 at 04:42:54PM +0300, Andy Shevchenko wrote:
> > > Some devices would need to have a hierarchy of properties and
> > > chil
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