setup: DMA
engine initialization failed
[ 6630.902835] meson8b-dwmac c941.ethernet eth0: stmmac_open: Hw setup
failed
Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset
GPIO bindings")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
---
arch/ar
d2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial
device-tree")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g1
5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY
reset line")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/am
ialization failed
[ 34.687850] meson8b-dwmac ff3f.ethernet eth0: stmmac_open: Hw setup
failed
Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY
reset line")
Reviewed-by: Martin Blumenstingl
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/
c6e82e5341 ("ARM: dts: meson: switch to the generic Ethernet PHY reset
bindings")
Reviewed-by: Martin Blumenstingl
Tested-by: Martin Blumenstingl # on
Odroid-C1+
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/meson8b-odroidc1.dts| 2 +-
arch/arm/boot/dts/meson8m2-mxiii-plus
On 2020-12-05 14:04, Martin Blumenstingl wrote:
> Hi Stefan,
>
> On Tue, Dec 1, 2020 at 2:21 PM Stefan Agner wrote:
>>
>> According to the datasheet (Rev. 1.9) the RTL8211F requires at least
>> 72ms "for internal circuits settling time" before accessing t
5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY
reset line")
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
b
d2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial
device-tree")
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
b/arch/arm64/boot/dt
c6e82e5341 ("ARM: dts: meson: switch to the generic Ethernet PHY reset
bindings")
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/meson8b-odroidc1.dts| 2 +-
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/
ialization failed
[ 34.687850] meson8b-dwmac ff3f.ethernet eth0: stmmac_open: Hw setup
failed
Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY
reset line")
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +
setup: DMA
engine initialization failed
[ 6630.902835] meson8b-dwmac c941.ethernet eth0: stmmac_open: Hw setup
failed
Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset
GPIO bindings")
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-gxb
On 2020-12-01 09:31, Jerome Brunet wrote:
> On Tue 01 Dec 2020 at 01:25, Stefan Agner wrote:
>
>> According to the datasheet (Rev. 1.4, page 30) the RTL8211F requires
>> at least 50ms "for internal circuits settling time" before accessing
>> the PHY re
MA
engine initialization failed
[ 34.687850] meson8b-dwmac ff3f.ethernet eth0: stmmac_open: Hw setup
failed
Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY
reset line")
Signed-off-by: Stefan Agner
---
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2
[adding Russell King for ARM]
On 2020-11-10 12:21, Arnd Bergmann wrote:
> On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport wrote:
>> > >
>> > > asm/sparsemem.h is not available on some architectures.
>> > > It's better to use linux/mmzone.h instead.
>
> Ah, I missed that, too.
>
>> > Hm,
On 2020-11-08 07:46, Mike Rapoport wrote:
> On Sat, Nov 07, 2020 at 04:22:06PM +0100, Stefan Agner wrote:
>> Most architectures define MAX_PHYSMEM_BITS in asm/sparsemem.h and don't
>> include it in asm/pgtable.h. Include asm/sparsemem.h directly to get
>> the MAX_PHYSM
On 2020-11-08 01:56, Andrew Morton wrote:
> On Sat, 7 Nov 2020 16:22:06 +0100 Stefan Agner wrote:
>
>> Most architectures define MAX_PHYSMEM_BITS in asm/sparsemem.h and don't
>> include it in asm/pgtable.h. Include asm/sparsemem.h directly to get
>> the MAX_PH
bfc0: 0003d2e0 b6f7b6f0 0076 befcbb20 befcbb28
bfe0: b6f4e060 befcbad8 b6f23e0c b6dc4a80
Code: e5927000 e0050391 e0871005 e5918018 (e5983000)
Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation library")
Signed-off-by: Stefan Agne
Hi Peter,
On 2020-10-04 15:31, Peter Geis wrote:
> Good Day,
>
> This series introduces upstream kernel support for the Ouya game
> console device. Please review and apply. Thank you in advance.
Interesting patchset, maybe I can give my Ouya a second live now :-) Do
you happen to have (a link)
On 2020-10-01 10:12, Miquel Raynal wrote:
> Hi Jann,
>
> Jann Horn wrote on Thu, 1 Oct 2020 00:32:24 +0200:
>
>> On Wed, Sep 30, 2020 at 11:30 PM Gustavo A. R. Silva
>> wrote:
>> > On Wed, Sep 30, 2020 at 11:10:43PM +0200, Jann Horn wrote:
>> > > On Wed, Sep 30, 2020 at 11:02 PM Gustavo A. R.
On 2020-09-08 16:16, Stefan Agner wrote:
> The lcdif IP does not support a framebuffer pitch (stride) other than
> framebuffer width. Check for equality and reject the framebuffer
> otherwise.
>
> This prevents a distorted picture when using 640x800 and running the
> Mesa gr
On 2020-09-08 10:48, Daniel Vetter wrote:
> On Tue, Sep 08, 2020 at 11:18:25AM +0300, Tomi Valkeinen wrote:
>> Hi,
>>
>> On 08/09/2020 10:55, Stefan Agner wrote:
>> > On 2020-09-07 20:18, Daniel Vetter wrote:
>> >> On Mon, Sep 07, 2020 at 07:17:12PM +0300
at that particular resolution to width != stride. Currently
Mesa has no fallback behavior, but rejecting this configuration allows
userspace to handle the issue correctly.
Fixes: 45d59d704080 ("drm: Add new driver for MXSFB controller")
Signed-off-by: Stefan Agner
Reviewed-by: Lauren
On 2020-09-08 14:33, Laurent Pinchart wrote:
> On Tue, Sep 08, 2020 at 02:29:02PM +0200, Daniel Vetter wrote:
>> On Tue, Sep 8, 2020 at 2:07 PM Stefan Agner wrote:
>> > On 2020-09-08 10:48, Daniel Vetter wrote:
>> >> On Tue, Sep 08, 2020 at 11:18:25AM +0300, Tomi Va
at that particular resolution to width != stride. Currently
Mesa has no fallback behavior, but rejecting this configuration allows
userspace to handle the issue correctly.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 21 -
1 file changed, 20 insertions(+), 1
On 2020-09-07 20:18, Daniel Vetter wrote:
> On Mon, Sep 07, 2020 at 07:17:12PM +0300, Laurent Pinchart wrote:
>> Hi Stefan,
>>
>> Thank you for the patch.
>>
>> On Mon, Sep 07, 2020 at 06:03:43PM +0200, Stefan Agner wrote:
>> > The lcdif IP does not suppo
at that particular resolution to width != stride. Currently
Mesa has no fallback behavior, but rejecting this configuration allows
userspace to handle the issue correctly.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions
disabled which leads to a system freeze.
Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Cc: Marek Szyprowski
Signed-off-by: Stefan Agner
Tested-by: Anand Moon
---
drivers/clk/me
disabled which leads to a system freeze.
Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.
Signed-off-by: Stefan Agner
---
drivers/clk/meson/g12a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index
ta...@vger.kernel.org
> Signed-off-by: Chris Healy
Reviewed-by: Stefan Agner
> ---
> Changes in v4:
> - Point to the appropriate commit for the Fixes: line
> - Update the Required Properties to add the "syscon" compatible
> ---
> Documentation/devicetree/bindin
On 2020-08-21 16:13, Chris Healy wrote:
> On Fri, Aug 21, 2020 at 6:21 AM Stefan Agner wrote:
>>
>> On 2020-08-20 06:10, Chris Healy wrote:
>> > From: Chris Healy
>> >
>> > Add syscon compatibility with Vybrid ocotp node. This is required to
>> &g
Hi Matthias,
On 2020-08-20 12:58, Matthias Schiffer wrote:
> The PIXCLK needs to be enabled in SCFG before accessing the DCU on LS1021A,
> or the access will hang.
Hm, this seems a rather ad-hoc access to SCFG from the DCU. We do
support a pixel clock in the device tree bindings of fsl-dcu, so
On 2020-08-20 06:10, Chris Healy wrote:
> From: Chris Healy
>
> Add syscon compatibility with Vybrid ocotp node. This is required to
> access the UID.
Hm, it seems today the SoC driver uses the specific compatible. It also
should expose the UID as soc_id, see drivers/soc/imx/soc-imx.c.
Maybe
Hi Christian,
On 2020-07-19 16:10, Christian Hewitt wrote:
> HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher
> clock speeds than the original ODROID-N2. Hardkernel supports the big cpu
> cluster at 2.4GHz and the little cpu cluster at 2.0GHz. Opp points and
> regulator
On 2020-07-18 19:14, Guido Günther wrote:
> Hi,
> On Mon, Mar 23, 2020 at 04:51:05PM +0100, Lucas Stach wrote:
>> Am Montag, den 23.03.2020, 15:52 +0100 schrieb Guido Günther:
>> > In contrast to other display controllers on imx like DCSS and ipuv3
>> > lcdif/mxsfb does not support detiling e.g.
On 2020-06-11 14:23, Bernard Zhao wrote:
> There are three err return values in drm_fbdev_generic_setup.
> In mxsfb_probe we called this function, but didn`t handle the
> return value, this change is to add err handle, maybe make code
> a bit more readable.
This got recently changed, so I guess
the appropriate FPU version.
This allows to build these macros with GNU assembler as well as with
Clang's built-in assembler.
[0] https://reviews.llvm.org/D59733
Link: https://github.com/ClangBuiltLinux/linux/issues/905
Signed-off-by: Stefan Agner
---
Changes in v3:
- Reworded commit message, adding hint
://reviews.llvm.org/D59733
Stefan Agner (3):
ARM: use .fpu assembler directives instead of assembler arguments
ARM: use VFP assembler mnemonics in register load/store macros
ARM: use VFP assembler mnemonics if available
arch/arm/Kconfig | 2 ++
arch/arm/Kconfig.assembler
use of .fpu directives and UAL VFP mnemonics for
register access.
This allows to build vfpmodule.c with Clang and its integrated assembler.
[0] https://reviews.llvm.org/D59733
Link: https://github.com/ClangBuiltLinux/linux/issues/905
Signed-off-by: Stefan Agner
---
Changes in v3:
- Reworded commit
github.com/ClangBuiltLinux/linux/issues/762
Signed-off-by: Stefan Agner
---
Changes in V3:
- Drop unnecessary comma
- Add .fpu directive also in single precision macros to avoid Clang error
error: instruction requires: fp registers
Changes in v2:
- Add link in commit message
arch/arm/vfp/Mak
On 2020-06-26 10:05, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache@40006000: $nodename:0:
> 'l2-cache@40006000' does not match
> '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Stefan
On 2019-10-21 07:41, Andreas Kemnade wrote:
> Add an RTC driver for the RTC device on Ricoh MFD rc5t619,
> which is implemented as a variant of rn5t618
>
> Signed-off-by: Andreas Kemnade
> ---
> drivers/rtc/Kconfig | 10 +
> drivers/rtc/Makefile | 1 +
> drivers/rtc/rtc-rc5t619.c
ter description UARTMODIR_* instead of
UARTMODEM_*. The value is the same, so there is no functional change.
Otherwise looks good to me:
Reviewed-by: Stefan Agner
--
Stefan
>
> Signed-off-by: Philippe Schenker
> ---
>
> drivers/tty/serial/fsl_lpuart.c | 4 ++--
> 1 file change
gt; Acked-by: Lorenzo Pieralisi
> Signed-off-by: Thierry Reding
Looks good to me! And helps also in my case, a board which has a broken
PSCI reset capability.
Reviewed-by: Stefan Agner
--
Stefan
> ---
> drivers/firmware/psci/psci.c | 12 ++--
> 1 file changed, 10 inserti
Hi Sudeep,
On 2019-10-14 12:07, Sudeep Holla wrote:
> On Sat, Oct 12, 2019 at 11:47:35PM +0200, Stefan Agner wrote:
>> From: Stefan Agner
>>
>> Use the kernels restart handler to register the PSCI system reset
>> capability. The restart handler use notifier chai
From: Stefan Agner
Use the kernels restart handler to register the PSCI system reset
capability. The restart handler use notifier chains along with
priorities. This allows to use restart handlers with higher priority
(in case available) while still supporting PSCI.
Since the ARM handler had
On 2019-08-29 21:34, Nathan Chancellor wrote:
> On Thu, Aug 29, 2019 at 10:55:28AM -0700, Nick Desaulniers wrote:
>> On Wed, Aug 28, 2019 at 11:27 PM Nathan Chancellor
>> wrote:
>> >
>> > Currently, multi_v7_defconfig + CONFIG_FUNCTION_TRACER fails to build
>> > with clang:
>> >
>> >
ps://github.com/llvm/llvm-project/commit/16fa8b09702378bacfa3d07081afe6b353b99e60
> Signed-off-by: Nathan Chancellor
Reviewed-by: Stefan Agner
--
Stefan
> ---
> arch/arm/Makefile | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/Makefile b/arch/arm/Mak
On 2019-08-08 15:14, Takashi Iwai wrote:
> On Thu, 08 Aug 2019 15:02:17 +0200,
> Mark Brown wrote:
>>
>> On Thu, Aug 08, 2019 at 03:00:06PM +0200, Takashi Iwai wrote:
>> > Mark Brown wrote:
>>
>> > > No, they absolutely should tell the user why they are deferring so the
>> > > user has some
On 2019-08-08 14:44, Mark Brown wrote:
> On Thu, Aug 08, 2019 at 02:36:55PM +0200, Stefan Agner wrote:
>> From: Stefan Agner
>>
>> Deferred probes shouldn't cause error messages in the boot log. Avoid
>> printing with dev_err() in case EPROBE_DEFER is the return valu
From: Stefan Agner
Deferred probes shouldn't cause error messages in the boot log. Avoid
printing with dev_err() in case EPROBE_DEFER is the return value.
Signed-off-by: Stefan Agner
---
sound/soc/soc-core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/sound/soc/soc
Enable deprecated/obsolete ARMv8 instructions emulation. This allows
to run ARMv6 binaries (e.g. Raspberry Pi) on ARMv8 machines.
Signed-off-by: Stefan Agner
---
arch/arm64/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64
On 2019-07-31 16:52, Philippe Schenker wrote:
> On Wed, 2019-07-31 at 09:56 -0300, Fabio Estevam wrote:
>> On Wed, Jul 31, 2019 at 9:38 AM Philippe Schenker
>> wrote:
>> > From: Stefan Agner
>> >
>> > Add pinmuxing and do not specify voltage restric
On 2019-07-26 16:46, Dmitry Osipenko wrote:
> 26.07.2019 17:23, Stefan Agner пишет:
>> Hi Thierry, Hi Dave,
>>
>> On 2018-09-07 01:31, Stefan Agner wrote:
>>> On 26.07.2018 06:36, Stefan Agner wrote:
>>>> If the GPIO subsystem is not ready make sure to ret
] Unhandled fault: imprecise external abort (0x1406) at
0xb6ea7000
...
[ 100.056423] PC is at dw_pcie_read+0x50/0x84
[ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48
...
Signed-off-by: Stefan Agner
---
Changes in v3:
- Rebase on pci/dwc
Changes in v4:
- Rebase on pci/dwc
Changes in v5
On 2019-05-14 16:38, Igor Opaniuk wrote:
> Introduce DTS for Colibri iMX6S/DL V1.1x re-design, where UHS-I support was
> added. Provide proper configuration for VGEN3, which allows that rail to
> be automatically switched to 1.8 volts for proper UHS-I operation mode.
>
> Signed-off-by: Igor
On 06.06.2019 11:06, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Allows to use the SD interface at a higher speed mode if the card
> supports it. For this the signaling voltage is switched from 3.3V to
> 1.8V under the usdhc1's drivers control.
>
> Signed-off-by: Igor Opaniuk
> ---
>
On 30.05.2019 22:02, Nick Desaulniers wrote:
> On Mon, May 27, 2019 at 3:41 PM Stefan Agner wrote:
>>
>> OMAP2 depends on ARCH_MULTI_V6, which makes sure that the kernel is
>> compiled with -march=armv6. The compiler frontend will pass the
>> architecture to the asse
is available since binutils 2.21 according to
its documentation [1].
[0] https://bugs.llvm.org/show_bug.cgi?id=40186
[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html
Signed-off-by: Stefan Agner
Acked-by: Mans Rullgard
Acked-by: Arnd Bergmann
Acked-by: Krzysztof Kozlowski
--
OMAP2 depends on ARCH_MULTI_V6, which makes sure that the kernel is
compiled with -march=armv6. The compiler frontend will pass the
architecture to the assembler. There is no explicit architecture
specification necessary.
Signed-off-by: Stefan Agner
Acked-by: Tony Lindgren
---
Changes since v2
On 15.04.2019 14:28, Arnd Bergmann wrote:
> On Sun, Apr 14, 2019 at 3:35 PM Russell King - ARM Linux admin
> wrote:
>
>> The subsequent hunks remove the defaulting of the choice according to
>> the function graph tracer - this is not a "hint" where the user can
>> still choose either option
On 11.04.2019 09:54, Stefan Agner wrote:
> The LLVM Target parser currently does not allow to specify the security
> extension as part of -march (see also LLVM Bug 40186 [0]). When trying
> to use Clang with LLVM's integrated assembler, this leads to build
> errors such as this:
>
->DATA_IN [64 B]
Reported-by: Sascha Hauer
Suggested-by: Boris Brezillon
Tested-by: Stefan Agner
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 50 +++-
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand
-by: Stefan Agner
Acked-by: Nicolas Pitre
---
arch/arm/mach-mvebu/pmsu_ll.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 88651221dbdd..c1fb713e9306 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
OMAP2 depends on ARCH_MULTI_V6, which makes sure that the kernel is
compiled with -march=armv6. The compiler frontend will pass the
architecture to the assembler. There is no explicit architecture
specification necessary.
Signed-off-by: Stefan Agner
---
Changes since v2:
- New patch
arch/arm
is available since binutils 2.21 according to
its documentation [1].
[0] https://bugs.llvm.org/show_bug.cgi?id=40186
[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html
Signed-off-by: Stefan Agner
Acked-by: Mans Rullgard
Acked-by: Arnd Bergmann
Acked-by: Krzysztof Kozlowski
--
, cr0, cr0, 5
^
arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
^
Signed-off-by: Stefan Agner
Acked-by: Nicolas Pitre
---
arch/arm/mach-mvebu/coherency_ll.S | 2 +-
arch/arm/mach-mvebu/pmsu_ll.S | 2 +-
2
-by: Stefan Agner
Signed-off-by: Stefan Agner
---
arch/arm/mach-imx/hotplug.c | 24 ++--
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index b35e99cc5e5b..7a74a9b89a49 100644
--- a/arch/arm/mach-imx
On 09.04.2019 16:50, Tony Lindgren wrote:
> Hi,
>
> * Stefan Agner [190408 20:59]:
>> --- a/arch/arm/mach-omap2/Makefile
>> +++ b/arch/arm/mach-omap2/Makefile
>> @@ -41,11 +41,6 @@ obj-$(CONFIG_SOC_OMAP5) +=
>> $(omap-4-5-com
On 09.04.2019 14:25, Måns Rullgård wrote:
> Stefan Agner writes:
>
>> The LLVM Target parser currently does not allow to specify the security
>> extension as part of -march (see also LLVM Bug 40186 [0]). When trying
>> to use Clang with LLVM's integrated assembler, this
t; - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
On 09.04.2019 14:25, Måns Rullgård wrote:
> Stefan Agner writes:
>
>> The LLVM Target parser currently does not allow to specify the security
>> extension as part of -march (see also LLVM Bug 40186 [0]). When trying
>> to use Clang with LLVM's integrated assembler, this
is available since binutils 2.21 according to
its documentation [1].
[0] https://bugs.llvm.org/show_bug.cgi?id=40186
[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html
Signed-off-by: Stefan Agner
Acked-by: Mans Rullgard
Acked-by: Arnd Bergmann
Acked-by: Krzysztof Kozlowski
--
-by: Stefan Agner
Acked-by: Nicolas Pitre
---
arch/arm/mach-mvebu/pmsu_ll.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 88651221dbdd..c1fb713e9306 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
, cr0, cr0, 5
^
arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
^
Signed-off-by: Stefan Agner
Acked-by: Nicolas Pitre
---
arch/arm/mach-mvebu/coherency_ll.S | 2 +-
arch/arm/mach-mvebu/pmsu_ll.S | 2 +-
2
On 31.03.2019 19:34, Arnd Bergmann wrote:
> On Sun, Mar 24, 2019 at 3:06 AM Arnd Bergmann wrote:
>>
>> On Sat, Mar 23, 2019 at 4:52 PM Stefan Agner wrote:
>> >
>> > The LLVM Target parser currently does not allow to specify the security
>> > extension
On 23.03.2019 21:06, Arnd Bergmann wrote:
> On Sat, Mar 23, 2019 at 4:52 PM Stefan Agner wrote:
>>
>> The LLVM Target parser currently does not allow to specify the security
>> extension as part of -march (see also LLVM Bug 40186 [0]). When trying
>> to use Clang with
, cr0, cr0, 5
^
arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
^
Signed-off-by: Stefan Agner
---
arch/arm/mach-mvebu/coherency_ll.S | 2 +-
arch/arm/mach-mvebu/pmsu_ll.S | 2 +-
2 files changed, 2
-by: Stefan Agner
---
arch/arm/mach-mvebu/pmsu_ll.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 88651221dbdd..c1fb713e9306 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -56,7 +56,6 @@ ENDPROC
llvm.org/show_bug.cgi?id=40186
[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html
Signed-off-by: Stefan Agner
---
arch/arm/mach-bcm/Makefile | 3 ---
arch/arm/mach-bcm/bcm_kona_smc.c | 2 --
arch/arm/mach-exynos/Makefile | 4
arch/arm/mach-exynos/exynos-smc.S | 2 +-
On 20.03.2019 13:10, Axel Lin wrote:
> The regulator_desc never need to be modified, so define them as const as a
> hint to the compiler that they can go into .rodata.
>
> Signed-off-by: Axel Lin
Looks good to me.
Reviewed-by: Stefan Agner
--
Stefan
> ---
> drivers
On 18.03.2019 19:09, Nick Desaulniers wrote:
> On Sun, Mar 17, 2019 at 4:05 PM Stefan Agner wrote:
>>
>> Currently LLVM's integrated assembler does not recognize .w form
>> of the pld instructions (LLVM Bug 40972 [0]):
>>
>> ./arch/arm/include/asm/processor.h:
On 18.03.2019 08:41, Anson Huang wrote:
> Add i.MX TPM(Low Power Timer/Pulse Width Modulation Module) PWM binding.
>
> Signed-off-by: Anson Huang
> ---
> No changes.
> ---
> Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt | 19
> +++
> 1 file changed, 19 insertions(+)
>
to -mauto-it and use -mimplicit-it=always only.
[0]
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=529707530657a333a304c651c808ea630c955223
Signed-off-by: Stefan Agner
Reviewed-by: Nick Desaulniers
---
Changes in v2:
- Drop $(comma) since we are no longer use the call to as-option
ended when compiling an Thumb-2 kernel.
Drop the macro to work around LLVM Bug 40972 issue.
[0] https://bugs.llvm.org/show_bug.cgi?id=40972
Signed-off-by: Stefan Agner
---
Changes in v2:
- Reword commit message to reflect the fact that this is a work around
for LLVM.
arch/arm/include/asm/proce
On 06.03.2019 01:47, Nick Desaulniers wrote:
> On Tue, Mar 5, 2019 at 3:39 PM Robin Murphy wrote:
>>
>> Hi Stefan,
>>
>> On 2019-03-05 10:18 pm, Stefan Agner wrote:
>> > The W macro for generating wide instructions when targeting Thumb-2
>> > is not re
On 16.03.2019 16:39, Russell King - ARM Linux admin wrote:
> On Sat, Mar 16, 2019 at 01:33:58PM +0100, Marek Vasut wrote:
>> If you have a FS or partition table there, it does.
>> If you don't, I agree ... that's a problem.
>
> eMMC boot partitions are called mmcblkXbootY, and unless you have
On 06.03.2019 00:39, Robin Murphy wrote:
> Hi Stefan,
>
> On 2019-03-05 10:18 pm, Stefan Agner wrote:
>> The W macro for generating wide instructions when targeting Thumb-2
>> is not required for the preload data instructions (pld, pldw) since
>> they are only ava
On 05.03.2019 23:21, Nick Desaulniers wrote:
> On Tue, Mar 5, 2019 at 2:17 PM Stefan Agner wrote:
>>
>> The assembler option -mauto-it is no longer a valid option. It has
>> been removed from the documentation in July 2009, which is well
>> before the release date
The assembler option -mauto-it is no longer a valid option. It has
been removed from the documentation in July 2009, which is well
before the release date of the currently supported binutils version
2.20.
Signed-off-by: Stefan Agner
---
arch/arm/Makefile | 3 +--
1 file changed, 1 insertion
1 error generated.
Drop the macro to make sure non-wide variants of pld and pldw are
emitted in all cases.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/processor.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/i
would be to make kexec depend on MMU for
>> > ARM - but I'm afraid I don't really know.
>>
>> Yeah, I've disabled KEXEC in my testing config. All I do care about is
>> to test nommu specific code paths in MM code.
>>
>> > I only have very limited nommu ex
g/bugzilla/show_bug.cgi?id=88648
Signed-off-by: Stefan Agner
---
I missed this instance in my previous commits and realized only
after running some randconfig.
arch/arm/include/asm/uaccess.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/uaccess.
ot;.syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.
[0]
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org
On 26.02.2019 13:21, Aisheng Dong wrote:
>> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
>> Sent: Saturday, February 23, 2019 1:01 AM
>>
>> In the iMX7d datasheet, the PAD_CTL_DSE_X* values are different from the
>> documentation.
>>
>
> It's a doc problem.
> Latest RM seems got
] Unhandled fault: imprecise external abort (0x1406) at
0xb6ea7000
...
[ 100.056423] PC is at dw_pcie_read+0x50/0x84
[ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48
...
Signed-off-by: Stefan Agner
---
Changes in v3:
- Rebase on pci/dwc
Changes in v4:
- Rebase on pci/dwc
Changes in v5
On 25.02.2019 17:52, Trent Piepho wrote:
> On Mon, 2019-02-25 at 16:15 +, Leonard Crestez wrote:
>> On Mon, 2019-02-25 at 17:02 +0100, Stefan Agner wrote:
>> > Define the length of the DBI registers and limit config space to its
>> > length. This makes sure that
On 25.02.2019 21:19, Bjorn Helgaas wrote:
> [+cc Thinh]
>
> On Mon, Feb 25, 2019 at 10:52 AM Trent Piepho wrote:
>> On Mon, 2019-02-25 at 16:15 +, Leonard Crestez wrote:
>> > On Mon, 2019-02-25 at 17:02 +0100, Stefan Agner wrote:
>> > > Define the length o
] Unhandled fault: imprecise external abort (0x1406) at
0xb6ea7000
...
[ 100.056423] PC is at dw_pcie_read+0x50/0x84
[ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48
...
Signed-off-by: Stefan Agner
---
Changes in v3:
- Rebase on pci/dwc
Changes in v4:
- Rebase on pci/dwc
Changes in v5
On 25.02.2019 15:47, Leonard Crestez wrote:
> On Mon, 2019-02-25 at 15:25 +0100, Stefan Agner wrote:
>> Define the length of the DBI registers and limit config space to its
>> length. This makes sure that the kernel does not access registers
>> beyond that point, avoidin
] Unhandled fault: imprecise external abort (0x1406) at
0xb6ea7000
...
[ 100.056423] PC is at dw_pcie_read+0x50/0x84
[ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48
...
Signed-off-by: Stefan Agner
---
Changes in v3:
- Rebase on pci/dwc
Changes in v4:
- Rebase on pci/dwc
Changes in v5
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