On Sat, Dec 26, 2020 at 01:51:28AM +0100, Konrad Dybcio wrote:
Konrad,
> Hi, are you going to resubmit this patch? Looks like
> MDM9607 uses Stromer PLL for its CPU clocks and could
> benefit from it.
Yes. But will take some time since we are held up with
additional activities.
Thanks
Varada
On Mon, Sep 28, 2020 at 01:10:18PM -0500, Rob Herring wrote:
> On Mon, 28 Sep 2020 10:45:37 +0530, Varadarajan Narayanan wrote:
> > Add device tree binding Documentation details for ipq5018
> > pinctrl driver.
> >
> > Signed-off-by: Varadarajan Narayanan
> > -
On Mon, Sep 28, 2020 at 01:43:22PM -0500, Bjorn Andersson wrote:
> On Mon 28 Sep 00:15 CDT 2020, Varadarajan Narayanan wrote:
> > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c
> > b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
> [..]
> > +static const struct msm_fu
Add initial device tree support for the Qualcomm IPQ5018 SoC and
MP03.1-C2 board.
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30
This patch adds support for the global clock controller found on
the IPQ5018 based devices.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/clock/qcom,gcc.yaml| 3 +
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings
Enables clk & pinctrl related configs
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6d04b95..ca25f79 100644
--- a/arch/arm64/configs/defconfig
+
Add programming sequence support for managing the Stromer
PLLs.
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/clk-alpha-pll.c | 156 ++-
drivers/clk/qcom/clk-alpha-pll.h | 5 ++
2 files changed, 160 insertions(+), 1 deletion(-)
diff --git
Add device tree binding Documentation details for ipq5018
pinctrl driver.
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq5018-pinctrl.yaml | 143 +
1 file changed, 143 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl
This adds the pinctrl definitions for the TLMM of IPQ5018.
Signed-off-by: Varadarajan Narayanan
---
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 903 +
3 files changed
The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq5018-mp03.1-c2 board.
Varadarajan Narayanan (7):
clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
dt-bindings: arm64: ipq5018: Add binding descriptions
Add support for the global clock controller found on IPQ5018
based devices.
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq5018.c | 3833
include/linux
q4019-ap.dk04.1-c1.dts | 20
> 2 files changed, 21 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>
NAND, BAM and SPI work fine.
Tested-by: Varadarajan Narayanan <var...@codeaurora.org>
-Varada
> diff --git a/arch/arm/boot/dts/
ged, 21 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>
NAND, BAM and SPI work fine.
Tested-by: Varadarajan Narayanan
-Varada
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ade7a38..b6c62c6 100644
> --- a/arch/a
On Fri, Aug 18, 2017 at 12:59:50PM +0530, Varadarajan Narayanan wrote:
> v9:
> Incorporate Stanimir's feedback for
> PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Forgot to mention that the patches were rebased against
Bjorn's pci.git/next.
Thanks
Varada
> Add St
On Fri, Aug 18, 2017 at 12:59:50PM +0530, Varadarajan Narayanan wrote:
> v9:
> Incorporate Stanimir's feedback for
> PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Forgot to mention that the patches were rebased against
Bjorn's pci.git/next.
Thanks
Varada
> Add St
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Varadarajan Narayana
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci
.
Acked-by: Stanimir Varbanov <svarba...@mm-sol.com>
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 210 +++-
1 file changed, 209 inserti
.
Acked-by: Stanimir Varbanov
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 210 +++-
1 file changed, 209 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Acked-by: Stanimir Varbanov <svarba...@mm-sol.com>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Acked-by: Stanimir Varbanov
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 138
nitions required to enable QMP phy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qc
hy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for opera
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c
port for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for operatio
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 132 +++-
1 file
he IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for operations
dt-bindings: pci: qcom: A
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
.../devicetree/bindin
.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 208
1 file changed, 208 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 208
1 file changed, 208 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index c4cd039..1cb03dd 100644
--- a/drivers
Stanimir,
> Hi,
>
> Thanks for the patch.
>
> On 31.07.2017 09:34, Varadarajan Narayanan wrote:
> >Add support for the IPQ8074 PCIe controller. IPQ8074 supports
> >Gen 1/2, one lane, two PCIe root complex with support for MSI and
> >legacy interrupts, and it
Stanimir,
> Hi,
>
> Thanks for the patch.
>
> On 31.07.2017 09:34, Varadarajan Narayanan wrote:
> >Add support for the IPQ8074 PCIe controller. IPQ8074 supports
> >Gen 1/2, one lane, two PCIe root complex with support for MSI and
> >legacy interrupts, and it
.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 233
1 file changed, 233 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
.../devicetree/bindin
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 233
1 file changed, 233 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index c4cd039..5bfbbd3 100644
--- a/drivers
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 132 +++-
1 file
CIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for operations
dt-bindings: pci: qcom: Add support for IPQ8074
PCI: dwc: qcom: Add support for IPQ8074
and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for operations
dt-bindings: pci: qcom: Add support for IPQ8074
PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
.../devicetree/bindings/pci/qco
PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (7):
dt-bindings: phy: qmp: Add output-clock-names
dt-bindings: phy: qmp: Add support for QMP phy in IPQ
, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (7):
dt-bindings: phy: qmp: Add output-clock-names
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
phy: qcom-qmp: Fix phy pipe
.
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b
.
Reviewed-by: Vivek Gautam
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..3dd7891 100644
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 12
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 124 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 133 +++-
1 file
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff
.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 245
1 file changed, 245 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 245
1 file changed, 245 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 6525f2f..b2ea953 100644
--- a/drivers
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
.../devicetree/bindin
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Reviewed-by: Vivek Gautam
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff --git
.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 245
1 file changed, 245 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 245
1 file changed, 245 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 6525f2f..b2ea953 100644
--- a/drivers
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 12
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 124 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
.../devicetree/bindin
hy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (7):
dt-bindings: phy: qmp: Add output-clock-
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
hy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (7):
dt-bindings: phy: qmp: Add output-clock-
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c
.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..4
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp
.
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..464049c 100644
--- a/drivers/phy
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 133 +++-
1 file
ed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 118 +++---
1 file changed, 55 insertions(+), 63 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index c0d4def..abe799b 100644
--- a/drivers/spi/spi
To operate in DMA mode, the buffer should be aligned and
the size of the transfer should be a multiple of block size
(for v1). And the no. of words being transferred should
be programmed in the count registers appropriately.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Andy Gross <andy.gr...@linaro.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index fdd34c3..f1aa5c1 100644
-
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index fdd34c3..f1aa5c1 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
controller->xfer = NULL and
restores it in the ISR. This looks to be some debug code which is not
required.
Signed-off-by: Andy Gross <andy.gr...@linaro.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 27 +--
1
controller->xfer = NULL and
restores it in the ISR. This looks to be some debug code which is not
required.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/driv
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index f1aa5c1..ef95294 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index f1aa5c1..ef95294 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -311,8 +311,8 @@ static
be no functional change
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-qup
be no functional change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index ff5aa08..1aa6078 100644
Much like the block mode changes, we are breaking up DMA transactions
into 64K chunks so we can reset the QUP engine.
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/sp
Much like the block mode changes, we are breaking up DMA transactions
into 64K chunks so we can reset the QUP engine.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 92 ---
1 file changed, 66
Use of_device_get_match_data to identify QUP version instead
of of_device_is_compatible.
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi
;mmccl...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 128 +++---
1 file changed, 80 insertions(+), 48 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1
Use of_device_get_match_data to identify QUP version instead
of of_device_is_compatible.
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 4c3c938..1364516
ned-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 128 +++---
1 file changed, 80 insertions(+), 48 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1aa6078..707b1ec 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/
k Sahu <abs...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 3c2c2c0..4c3c938 100644
--- a/dri
Take specific sgl and nent to be prepared. This is in
preparation for splitting DMA into multiple transacations, this
contains no code changes just refactoring.
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 3c2c2c0..4c3c938 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -266,7 +266,7 @@ static void
Take specific sgl and nent to be prepared. This is in
preparation for splitting DMA into multiple transacations, this
contains no code changes just refactoring.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 23 ++-
1
This patch corrects the behavior of the BLOCK
transactions. During block transactions, the controller
must be read/written to in block size transactions.
Signed-off-by: Andy Gross <andy.gr...@linaro.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/s
This patch corrects the behavior of the BLOCK
transactions. During block transactions, the controller
must be read/written to in block size transactions.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 151
refactoring, there should be no functional
change
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 91 +++
1 file changed, 62 insertions(+),
Add i/o completion timeout for DMA and PIO modes.
Signed-off-by: Andy Gross <andy.gr...@linaro.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/s
refactoring, there should be no functional
change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 91 +++
1 file changed, 62 insertions(+), 29 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers
Add i/o completion timeout for DMA and PIO modes.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index abe799b..fdd34c3
t versions of QUP,
re-enabling it for QUP versions later than v1.
Signed-off-by: Sham Muthayyan <smuth...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---
drivers/spi/spi-qup.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/d
1 - 100 of 509 matches
Mail list logo
