On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > +
> > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > > +{
> > > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(_dev->dev);
> > > > > > > > > +
> > > > > > > > >
On Thu, Apr 08, 2021 at 11:53:06AM -0700, Moritz Fischer wrote:
> On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > >
On Thu, Apr 08, 2021 at 05:20:19PM +0800, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > >
On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > >
> > > > Hi Matthew,
> > > >
> > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > matthew.gerl...@linux.intel.com wrote:
> > > > > From: Matthew Gerlach
> > > > >
> > > > > This patch
On Mon, Apr 05, 2021 at 04:53:01PM -0700, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> Like the Intel N3000 card, the Intel D5005 has a MAX10 based
> BMC. This commit adds support for the D5005 sensors that are
> monitored by the MAX10 BMC.
>
> Signed-off-by: Matthew
and go with next pull request?
Thanks,
Yilun
On Mon, Mar 08, 2021 at 09:59:34AM +0800, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in userspace.
>
> There are some Q about why UIO driver is needed in v11:
>
> >From Greg:
> Why are you saying th
Hi Greg:
I listed below some answers from Moritz and Yilun from previous mails for
your question.
Do you have more comments?
Thanks in advance,
Yilun
On Mon, Mar 08, 2021 at 09:59:34AM +0800, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in usersp
This patch fixes the max register address of MAX 10 BMC. The range
0x2000 ~ 0x20fc are for control registers of the QSPI flash
controller, which are not accessible to host.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-for-MFD-by: Lee Jones
---
v2: no change.
v3: no change
Rix as the reviewer for intel-m10-bmc mfd driver and the subdev
drivers.
- Rebased to 5.12-rc1
Main changes from v3:
- Improve the comments for valid version check.
Matthew Gerlach (1):
mfd: intel-m10-bmc: Add access table configuration to the regmap
Xu Yilun (3):
mfd: intel-m10-bmc: Fix
The version register is the only one in the legacy I/O space to be
accessed, so it is not necessary to define the legacy base & version
register offset. A direct definition of the legacy version register
address would be fine.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v3: no ch
From: Matthew Gerlach
This patch adds access tables to the MAX 10 BMC regmap. This prevents
the host from accessing the unwanted I/O space. It also filters out the
invalid outputs when reading the regmap debugfs interface.
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
Reviewed
This patch adds maintainer info for Intel MAX 10 mfd driver.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-for-MFD-by: Lee Jones
---
v3: Add Tom Rix as the reviewer.
v4: Add Lee's Acked-by, no other change.
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git
On Wed, Mar 10, 2021 at 09:16:25AM +, Lee Jones wrote:
> On Mon, 01 Mar 2021, Xu Yilun wrote:
>
> > The version register is the only one in the legacy I/O space to be
> > accessed, so it is not necessary to define the legacy base & version
> > register
On Mon, Mar 08, 2021 at 09:01:24AM +, Lee Jones wrote:
> On Mon, 08 Mar 2021, Xu Yilun wrote:
>
> > Hi Lee:
> >
> > Could you please help on review this patchset? They are some
> > improvements for intel-m10-bmc MFD driver.
>
> Please don't send conte
Hi Lee:
Could you please help on review this patchset? They are some
improvements for intel-m10-bmc MFD driver.
Thanks,
Yilun
On Mon, Mar 01, 2021 at 01:59:41PM +0800, Xu Yilun wrote:
> This patchset is some improvements for intel-m10-bmc and its subdevs.
>
> Main changes from v1
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Reviewed-by: Wu Hao
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve
e Feature List) bus device to
userspace, a DFL driver for UIO is needed to bind to it.
See the original message in:
https://lore.kernel.org/linux-fpga/ydvq8ao8v3nhl...@epycbox.lan/T/#m91b303fd61485644353fad1e1e9c11d528844684
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
This patch supports the DFL drivers be written in userspace. This is
realized by exposing the userspace I/O device interfaces.
The driver now only binds the ether group feature, which has no irq. So
the irq support is not implemented yet.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v9
This patch adds maintainer info for Intel MAX 10 mfd driver.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v3: Add Tom Rix as the reviewer.
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b58a469..ab31c01 100644
From: Matthew Gerlach
This patch adds access tables to the MAX 10 BMC regmap. This prevents
the host from accessing the unwanted I/O space. It also filters out the
invalid outputs when reading the regmap debugfs interface.
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
Reviewed
This patch fixes the max register address of MAX 10 BMC. The range
0x2000 ~ 0x20fc are for control registers of the QSPI flash
controller, which are not accessible to host.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v2: no change.
v3: no change, rebased to 5.12-rc1
---
include
Rix as the reviewer for intel-m10-bmc mfd driver and the subdev
drivers.
- Rebased to 5.12-rc1
Matthew Gerlach (1):
mfd: intel-m10-bmc: Add access table configuration to the regmap
Xu Yilun (3):
mfd: intel-m10-bmc: Fix the register access range
mfd: intel-m10-bmc: Simplify the legacy
The version register is the only one in the legacy I/O space to be
accessed, so it is not necessary to define the legacy base & version
register offset. A direct definition of the legacy version register
address would be fine.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v3: no ch
On Sat, Feb 27, 2021 at 04:42:55PM +0100, Greg KH wrote:
> On Sat, Feb 27, 2021 at 11:27:03PM +0800, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driv
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Reviewed-by: Wu Hao
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve
This patch supports the DFL drivers be written in userspace. This is
realized by exposing the userspace I/O device interfaces.
The driver now only binds the ether group feature, which has no irq. So
the irq support is not implemented yet.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v9
header, add detailed
path for opae uio example in Kconfig.
Main changes from v10:
- add description in doc that interrupt support is not implemented yet.
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
Documentation: fpga: dfl: Add description for DFL UIO s
Hi Greg:
On Fri, Feb 26, 2021 at 07:40:56AM +0100, Greg KH wrote:
> On Fri, Feb 26, 2021 at 09:22:37AM +0800, Xu Yilun wrote:
> > On Mon, Feb 22, 2021 at 10:56:45AM -0800, Tom Rix wrote:
> > > Yilun,
> > >
> > > Is there anything outstanding or remaining
) for pdev creation.
> >
> > Main changes from v7:
> > - some doc fixes.
> >
> > Main changes from v8:
> > - switch to add a uio driver in drivers/uio
> >
> > Main changes from v9:
> > - add this source file in MAINTAINERS
> > - improve the Kcon
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Reviewed-by: Wu Hao
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve
This patch supports the DFL drivers be written in userspace. This is
realized by exposing the userspace I/O device interfaces.
The driver now only binds the ether group feature, which has no irq. So
the irq support is not implemented yet.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v9
header, add detailed
path for opae uio example in Kconfig.
Main changes from v10:
- add description in doc that interrupt support is not implemented yet.
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
Documentation: fpga: dfl: Add description for DFL UIO s
On Mon, Feb 01, 2021 at 08:59:06PM +0800, Wu, Hao wrote:
> > Subject: [PATCH v10 2/2] Documentation: fpga: dfl: Add description for DFL
> > UIO
> > support
> >
> > This patch adds description for UIO support for dfl devices on DFL
> > bus.
> >
> > S
tive Kconfig header, add detailed
path for opae uio example in Kconfig.
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
Documentation: fpga: dfl: Add description for DFL UIO support
Documentation/fpga/dfl.rst | 23
MAINTAINERS| 1 +
drivers/uio/K
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title
This patch supports the DFL drivers be written in userspace. This is
realized by exposing the userspace I/O device interfaces.
The driver now only binds the ether group feature, which has no irq. So
the irq support is not implemented yet.
Signed-off-by: Xu Yilun
---
v9: switch to add a uio
On Tue, Jan 26, 2021 at 07:06:17AM -0800, Tom Rix wrote:
>
> On 1/25/21 10:50 PM, Xu Yilun wrote:
> > This patch adds maintainer info for Intel MAX 10 mfd driver.
> >
> > Signed-off-by: Xu Yilun
> > ---
> > MAINTAINERS | 9 +
> > 1 file c
mprovement.
Main changes from v6:
- use platform_device_register_resndata() for pdev creation.
Main changes from v7:
- some doc fixes.
Main changes from v9:
- switch to add a uio driver in drivers/uio
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
Documentation: fpga: dfl: Add description
This patch supports the DFL drivers be written in userspace. This is
realized by exposing the userspace I/O device interfaces.
The driver now only binds the ether group feature, which has no irq. So
the irq support is not implemented yet.
Signed-off-by: Xu Yilun
---
v9: switch to add a uio
This patch fixes the max register address of MAX 10 BMC. The range
0x2000 ~ 0x20fc are for control registers of the QSPI flash
controller, which are not accessible to host.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v2: no change.
---
include/linux/mfd/intel-m10-bmc.h | 2 +-
1
: intel-m10-bmc: Add access table configuration to the regmap
Xu Yilun (3):
mfd: intel-m10-bmc: Fix the register access range
mfd: intel-m10-bmc: Simplify the legacy version reg definition
MAINTAINERS: Add entry for Intel MAX 10 mfd driver
MAINTAINERS | 9
From: Matthew Gerlach
This patch adds access tables to the MAX 10 BMC regmap. This prevents
the host from accessing the unwanted I/O space. It also filters out the
invalid outputs when reading the regmap debugfs interface.
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
---
v2
This patch adds maintainer info for Intel MAX 10 mfd driver.
Signed-off-by: Xu Yilun
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5aa18cb..10985d3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9132,6 +9132,15 @@ F: include
The version register is the only one in the legacy I/O space to be
accessed, so it is not necessary to define the legacy base & version
register offset. A direct definition of the legacy version register
address would be fine.
Signed-off-by: Xu Yilun
---
drivers/mfd/intel-m10-bmc.c
On Mon, Jan 25, 2021 at 06:22:55PM -0800, Moritz Fischer wrote:
> On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
> >
> > On 1/25/21 12:49 AM, Xu Yilun wrote:
> > > This patch supports the DFL drivers be written in userspace. This is
> > > realized by
On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
>
> On 1/25/21 12:49 AM, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driver now only binds
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support
0100, Greg KH wrote:
> > >> On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
> > >>> This patch supports the DFL drivers be written in userspace. This is
> > >>> realized by exposing the userspace I/O device interfaces.
> > >>>
> >
On Thu, Jan 21, 2021 at 05:19:56AM -0800, Tom Rix wrote:
>
> On 1/21/21 12:05 AM, Xu Yilun wrote:
> > On Wed, Jan 20, 2021 at 07:32:53AM -0800, Tom Rix wrote:
> >> On 1/19/21 6:34 PM, Xu Yilun wrote:
> >>> From: Matthew Gerlach
> >>>
> >>&g
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support
in changes from v4:
- refactor the irq handling code.
Main changes from v5:
- fix the res[] zero initialization issue.
- improve the return code for probe().
- some doc improvement.
Main changes from v6:
- use platform_device_register_resndata() for pdev creation.
Main changes from v7:
- some doc fix
provide support to userspace access to kernel
interrupts and memory locations.
The driver now supports the ether group feature. To support a new DFL
feature been directly accessed via UIO, its feature id should be added to
the driver's id_table.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked
On Wed, Jan 20, 2021 at 07:32:53AM -0800, Tom Rix wrote:
>
> On 1/19/21 6:34 PM, Xu Yilun wrote:
> > From: Matthew Gerlach
> >
> > This patch adds access tables to the MAX 10 BMC regmap. This prevents
> > the host from accessing the unwanted I/O space. It also filte
On Wed, Jan 20, 2021 at 12:26:35AM -0800, Pan Bian wrote:
> Release master that have been previously allocated if the number of
> chipselect is invalid.
>
> Fixes: 8e04187c1bc7 ("spi: altera: add SPI core parameters support via
> platform data.")
> Signed-off-by: Pan Bian
> ---
>
From: Matthew Gerlach
This patch adds access tables to the MAX 10 BMC regmap. This prevents
the host from accessing the unwanted I/O space. It also filters out the
invalid outputs when reading the regmap debugfs interface.
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
---
drivers
On Tue, Jan 19, 2021 at 07:12:24PM -0800, Randy Dunlap wrote:
> Doc suggestions:
>
> On 1/19/21 6:43 PM, Xu Yilun wrote:
> > This patch adds description for UIO support for dfl devices on DFL
> > bus.
> >
> > Signed-off-by: Xu Yilun
> > ---
> >
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support
provide support to userspace access to kernel
interrupts and memory locations.
The driver now supports the ether group feature. To support a new DFL
feature been directly accessed via UIO, its feature id should be added to
the driver's id_table.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked
in changes from v4:
- refactor the irq handling code.
Main changes from v5:
- fix the res[] zero initialization issue.
- improve the return code for probe().
- some doc improvement.
Main changes from v6:
- use platform_device_register_resndata() for pdev creation.
Xu Yilun (2):
fpga: dfl: add th
This patch fixes the max register address of MAX 10 BMC. The range
0x2000 ~ 0x20fc are for control registers of the QSPI flash
controller, which are not accessible to host.
Signed-off-by: Xu Yilun
---
include/linux/mfd/intel-m10-bmc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On Sat, Jan 16, 2021 at 07:57:48PM -0800, Moritz Fischer wrote:
> Hi Xu,
>
> On Wed, Jan 13, 2021 at 09:54:08AM +0800, Xu Yilun wrote:
> > This patch adds description for UIO support for dfl devices on DFL
> > bus.
> >
> > Signed-off-by: Xu Yilun
> >
On Sat, Jan 16, 2021 at 07:56:08PM -0800, Moritz Fischer wrote:
> Hi Xu,
>
> On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support
provide support to userspace access to kernel
interrupts and memory locations.
The driver now supports the ether group feature. To support a new DFL
feature been directly accessed via UIO, its feature id should be added to
the driver's id_table.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked
in changes from v4:
- refactor the irq handling code.
Main changes from v5:
- fix the res[] zero initialization issue.
- improve the return code for probe().
- some doc improvement.
Xu Yilun (2):
fpga: dfl: add the userspace I/O device support for DFL devices
Documentation: fpga: dfl: Add d
On Mon, Jan 11, 2021 at 06:59:10AM -0800, Tom Rix wrote:
>
> On 1/10/21 10:16 PM, Xu Yilun wrote:
> > On Sun, Jan 10, 2021 at 12:11:17PM -0800, Moritz Fischer wrote:
> >> On Sat, Jan 02, 2021 at 11:13:01AM +0800, Xu Yilun wrote:
> >>> This patch supports the DF
On Sun, Jan 10, 2021 at 11:58:44AM -0800, Moritz Fischer wrote:
> Hi Xu,
>
> On Sat, Jan 02, 2021 at 11:13:00AM +0800, Xu Yilun wrote:
> > This patchset supports some dfl device drivers written in userspace.
> >
> > In the patchset v1, the "driver_override&q
On Sun, Jan 10, 2021 at 12:11:17PM -0800, Moritz Fischer wrote:
> On Sat, Jan 02, 2021 at 11:13:01AM +0800, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
>
On Thu, Jan 07, 2021 at 03:51:38PM +0100, Andrew Lunn wrote:
> On Thu, Jan 07, 2021 at 10:26:12AM +0100, Greg KH wrote:
> > On Thu, Jan 07, 2021 at 02:07:08PM +0800, Xu Yilun wrote:
> > > This driver supports the ethernet retimers (C827) for the Intel PAC
> > > (Pro
On Thu, Jan 07, 2021 at 10:26:12AM +0100, Greg KH wrote:
> On Thu, Jan 07, 2021 at 02:07:08PM +0800, Xu Yilun wrote:
> > This driver supports the ethernet retimers (C827) for the Intel PAC
> > (Programmable Acceleration Card) N3000, which is a FPGA based Smart NIC.
> >
&
10 BMC firmware. They are configured in 4 ports
10G/25G retimer mode. Host could query their link states and firmware
version information via retimer interfaces (Shared registers) on Intel
MAX 10 BMC. The driver creates sysfs interfaces for users to query these
information.
Signed-off-by: Xu Yilun
https://github.com/OPAE/opae-sdk/
Generally it facilitate the development on all the DFL (Device Feature
List) based FPGA Cards, including the management of static region &
dynamic region reprogramming, accelerators accessing and the board
specific peripherals.
Xu Yilun (2):
mfd: intel-m10-bm
query them via
retimer interfaces (shared registers) on the BMC. The 2 retimers have
identical register interfaces in different register addresses or fields,
so it is better we define 2 retimer devices and handle them with the same
driver.
Signed-off-by: Xu Yilun
---
drivers/mfd/intel-m10-bmc.c
On Wed, Jan 06, 2021 at 08:23:30AM +, Lee Jones wrote:
> On Wed, 06 Jan 2021, Xu Yilun wrote:
>
> > The patch specifies the 2 retimer sub devices and their resources in the
> > parent driver's mfd_cell. It also adds the register definition of the
> > retimer sub devic
On Wed, Jan 06, 2021 at 10:06:14AM +0100, Greg KH wrote:
> On Wed, Jan 06, 2021 at 04:53:29PM +0800, Xu Yilun wrote:
> > On Wed, Jan 06, 2021 at 08:56:42AM +0100, Greg KH wrote:
> > > On Wed, Jan 06, 2021 at 03:36:07PM +0800, Xu Yilun wrote:
> > > > This driver suppor
On Wed, Jan 06, 2021 at 08:56:42AM +0100, Greg KH wrote:
> On Wed, Jan 06, 2021 at 03:36:07PM +0800, Xu Yilun wrote:
> > This driver supports the ethernet retimers (C827) for the Intel PAC
> > (Programmable Acceleration Card) N3000, which is a FPGA based Smart NIC.
> >
&
10 BMC firmware. They are configured in 4 ports
10G/25G retimer mode. Host could query their link states and firmware
version information via retimer interfaces (Shared registers) on Intel
MAX 10 BMC. The driver creates sysfs interfaces for users to query these
information.
Signed-off-by: Xu Yilun
query them via
retimer interfaces (shared registers) on the BMC. The 2 retimers have
identical register interfaces in different register addresses or fields,
so it is better we define 2 retimer devices and handle them with the same
driver.
Signed-off-by: Xu Yilun
---
drivers/mfd/intel-m10-bmc.c
version information via retimer interfaces (Shared registers) on
the BMC. The driver creates sysfs interfaces for users to query these
information.
Xu Yilun (2):
mfd: intel-m10-bmc: specify the retimer sub devices
misc: add support for retimers interfaces on Intel MAX 10 BMC
.../ABI/testing
On Mon, Jan 04, 2021 at 09:19:24AM -0800, Russ Weight wrote:
>
>
> On 1/1/21 7:13 PM, Xu Yilun wrote:
> > This patch adds description for UIO support for dfl devices on DFL
> > bus.
> >
> > Signed-off-by: Xu Yilun
> > ---
> > v2: no doc in v1, ad
On Mon, Jan 04, 2021 at 12:24:05PM +0800, Wu, Hao wrote:
> > Subject: [PATCH v5 2/2] Documentation: fpga: dfl: Add description for DFL
> > UIO support
> >
> > This patch adds description for UIO support for dfl devices on DFL
> > bus.
> >
> > Signed-off-
memory locations.
> >
> > The driver now supports the ether group feature. To support a new DFL
> > feature been directly accessed via UIO, its feature id should be added to
> > the driver's id_table.
> >
> > Signed-off-by: Xu Yilun
> > Reviewed-by: Tom R
The xfer waiting time is the result of xfer->len / xfer->speed_hz. This
patch makes the assumption of 100khz xfer speed if the xfer->speed_hz is
not assigned and stays 0. This avoids the divide by 0 issue and ensures
a reasonable tolerant waiting time.
Signed-off-by: Xu Yilun
--
On Sat, Jan 02, 2021 at 11:11:14AM -0300, Fabio Estevam wrote:
> On Sat, Jan 2, 2021 at 12:07 AM Xu Yilun wrote:
> >
> > The xfer waiting time is the result of xfer->len / xfer->speed_hz. This
> > patch makes the assumption of 1khz xfer speed if the xfer->speed_h
provide support to userspace access to kernel
interrupts and memory locations.
The driver now supports the ether group feature. To support a new DFL
feature been directly accessed via UIO, its feature id should be added to
the driver's id_table.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v2
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
---
Documentation/fpga/dfl.rst | 24
in changes from v4:
- refactor the irq handling code.
Xu Yilun (2):
fpga: dfl: add the userspace I/O device support for DFL devices
Documentation: fpga: dfl: Add description for DFL UIO support
Documentation/fpga/dfl.rst | 24
drivers/fpga/Kconfig| 10 +
drivers/fpga/
The xfer waiting time is the result of xfer->len / xfer->speed_hz. This
patch makes the assumption of 1khz xfer speed if the xfer->speed_hz is
not assigned and stays 0. This avoids the divide by 0 issue and ensures
a reasonable tolerant waiting time.
Signed-off-by: Xu Yilun
--
On Wed, Dec 30, 2020 at 01:46:44PM +, Mark Brown wrote:
> On Wed, Dec 30, 2020 at 10:24:20AM +0800, Xu Yilun wrote:
> > On Tue, Dec 29, 2020 at 01:13:08PM +, Mark Brown wrote:
>
> > > Does this still apply with current code? There have been some fixes in
> >
On Tue, Dec 29, 2020 at 06:37:37AM -0800, Tom Rix wrote:
>
> On 12/28/20 6:42 PM, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driver leverage
On Tue, Dec 29, 2020 at 01:13:08PM +, Mark Brown wrote:
> On Tue, Dec 29, 2020 at 01:27:42PM +0800, Xu Yilun wrote:
> > The xfer waiting time is the result of xfer->len / xfer->speed_hz, but
> > when the following patch is merged,
> >
> > commit 9326e4f1e5d
d ensures a
reasonable tolerant waiting time.
Signed-off-by: Xu Yilun
---
drivers/spi/spi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 51d7c00..2f3c2c9 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1109,6
transfer is finished, return 1 when transfer is still in
progress.
Signed-off-by: Xu Yilun
---
drivers/spi/spi-altera.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index 809bfff..cbc4c28 100644
tolerant waiting time in
a generic way.
Xu Yilun (2):
spi: altera: fix return value for altera_spi_txrx()
spi: fix the divide by 0 error when calculating xfer waiting time
drivers/spi/spi-altera.c | 26 ++
drivers/spi/spi.c| 4 +++-
2 files changed, 17 inser
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
---
Documentation/fpga/dfl.rst | 24
1 file
provide support to userspace access to kernel
interrupts and memory locations.
The driver now supports the ether group feature. To support a new DFL
feature been directly accessed via UIO, its feature id should be added to
the driver's id_table.
Signed-off-by: Xu Yilun
---
v2: switch to the new
the match ops changes in dfl.c to an independent patch.
- move the declarations needed for dfl-uio-pdev from include/linux/dfl.h
to driver/fpga/dfl.h
- some minor fixes.
Main changes from v3:
- switch to specifying each matching device in the driver's id_table.
- refactor the irq handling code.
is to be reprogrammed. This gives users a reliable method to
prevent potential data leakage.
Signed-off-by: Xu Yilun
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
Acked-by: Krzysztof Kozlowski
---
v2: Adjust the position of this driver in Kconfig.
Improves the name of the Kconfig option.
Change
SPI work.
[m...@kernel.org: Fixed up MAINTAINERS file to include added ABI doc]
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Signed-off-by: YueHaibing
Reviewed-by: Tom Rix
---
v3: add the doc for this driver
minor fixes
to match filename]
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
---
v2: updated the MAINTAINERS under FPGA DFL DRIVERS
improve the comments
rename the dfl-bus.h to dfl.h
v3: rebase the patch for previous changes
v9: rebase the patch for bus
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