RE: [PATCH] PCI: dwc: Change the inheritance between the abstracted structures

Hi Bjorn, Thanks a lot for the comments! > -Original Message- > From: Bjorn Helgaas > Sent: 2021年4月7日 1:09 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; > Kishon Vij

RE: [PATCH] PCI: dwc: Change the inheritance between the abstracted structures

Hi Lorenzo and All, Any comments on this patch? Thanks, Zhiqiang > -Original Message- > From: Z.q. Hou > Sent: 2021年1月29日 17:40 > To: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com > Cc: Z.q.

RE: [PATCH 0/4] PCI: dwc: Refine the EP code no functionality change

Hi Lorenzo, Rob and Bjorn, Any comments on this series? Thanks, Zhiqiang > -Original Message- > From: Z.q. Hou > Sent: 2021年1月7日 17:11 > To: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; linux-o...@vger.kernel.org;

RE: [PATCH 0/7] PCI: layerscape: Add power management support

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2021年3月23日 19:15 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelg...@google.com; robh...@kernel.org; > shawn...@kernel.org; Leo

RE: [PATCH] PCI: dwc: Move forward the iATU detection process

perspective initializations into hardware ones. Thanks Zhiqiang > -Original Message- > From: Kunihiko Hayashi > Sent: 2021年1月26日 13:26 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; > lorenzo.pieral...@arm.com; r...@kernel.org; b

RE: [PATCHv9] arm64: dts: layerscape: Add PCIe EP node for ls1088a

Hi Shawn, Thanks a lot for your comments! > -Original Message- > From: Shawn Guo > Sent: 2020年11月1日 16:55 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; robh...@kernel.org; Leo Li > ; Xiaow

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Lorenzo and Richard, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2020年10月20日 17:55 > To: Z.q. Hou > Cc: Kishon Vijay Abraham I ; Bjorn Helgaas > ; linux-kernel@vger.kernel.org; > linux-...@vger.kernel.org; r...@kernel.org; bhelg...@google

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Bjorn, Lorenzo and Kishon, > -Original Message- > From: Kishon Vijay Abraham I > Sent: 2020年10月19日 13:41 > To: Z.q. Hou ; Bjorn Helgaas > Cc: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; > r...@kernel.org; lorenzo.pieral...@arm.com; bhelg...@google.co

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hello Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas > Sent: 2020年10月16日 6:48 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; > r...@kernel.org; lorenzo.pieral...@arm.com; bhelg...@google.co

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Kishon, > -Original Message- > From: Kishon Vijay Abraham I > Sent: 2020年10月1日 21:32 > To: Rob Herring > Cc: Gustavo Pimentel ; Z.q. Hou > ; Lorenzo Pieralisi ; > linux-kernel@vger.kernel.org; PCI ; Bjorn > Helgaas ; Michael Walle ; Ard > Biesheuvel >

RE: [PATCH] PCI: layerscape: Change back to the default error response behavior

Hi Rob and Kishon, > -Original Message- > From: Rob Herring > Sent: 2020年9月30日 23:08 > To: Kishon Vijay Abraham I > Cc: Z.q. Hou ; PCI ; > linux-kernel@vger.kernel.org; linux-arm-kernel > ; Lorenzo Pieralisi > ; Bjorn Helgaas ; M.h. > Lian ; Roy Zang ; Mingk

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

> -Original Message- > From: Rob Herring > Sent: 2020年9月30日 1:11 > To: Gustavo Pimentel > Cc: Z.q. Hou ; Lorenzo Pieralisi > ; linux-kernel@vger.kernel.org; PCI > ; Bjorn Helgaas ; > Michael Walle ; Ard Biesheuvel > Subject: Re: [PATCH] PCI: dwc: Add

RE: [PATCH] PCI: layerscape: Change back to the default error response behavior

Hi Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas > Sent: 2020年9月29日 23:03 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; lorenzo.pieral...@arm.com; > r

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2020年9月28日 17:39 > To: Z.q. Hou > Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI > ; Bjorn Helgaas ; > Gustavo Pimentel ; Michael Walle > ; Ard Biesheuvel &g

RE: [PATCH v6 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding

Hi Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas > Sent: 2020年9月24日 4:16 > To: Xiaowei Bao > Cc: Z.q. Hou ; M.h. Lian > ; Mingkai Hu ; > bhelg...@google.com; robh...@kernel.org; shawn...@kernel.org; Leo Li > ; kis...@ti.com; l

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月18日 23:28 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; PCI ; Lorenzo > Pieralisi ; Bjorn Helgaas > ; Gustavo Pimentel > ; Michael Walle ; > Ard Biesheuvel

RE: [PATCH 6/7] dts: arm64: ls1043a: Add SCFG phandle for PCIe nodes

Hi Shawn, Thanks a lot for your comments! > -Original Message- > From: Shawn Guo > Sent: 2020年9月21日 21:17 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelg...@google.com; robh...@kernel.org; > Le

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas > Sent: 2020年9月18日 20:47 > To: Z.q. Hou > Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI > ; Lorenzo Pieralisi ; > Bjorn Helgaas ; Gustavo Pimentel > ; Michael Walle ; >

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Michael, Thanks a lot for your comments! > -Original Message- > From: Michael Walle > Sent: 2020年9月18日 19:14 > To: Z.q. Hou > Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI > ; Lorenzo Pieralisi ; > Bjorn Helgaas ; Gustavo Pimentel > ; Ard Biesheuvel &g

RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月17日 4:29 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; PCI ; Lorenzo > Pieralisi ; Bjorn Helgaas > ; Gustavo Pimentel > ; Michael Walle ; > Ard Biesheuvel

RE: [PATCHv7 04/12] PCI: designware-ep: Modify MSI and MSIX CAP way of finding

Hi Rob, > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 2:10 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linuxppc-...@lists.ozlabs.org

RE: [PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2020年9月18日 0:20 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infrade

RE: [PATCH 7/7] PCI: layerscape: Add power management support

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月15日 9:30 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelg...@google.com; > shawn...@kernel.org; Leo

RE: [PATCH 2/7] PCI: layerscape: Change to use the DWC common link-up check function

Hi Rob, Thanks a lot for your review! > -Original Message- > From: Rob Herring > Sent: 2020年9月15日 9:20 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelg...@google.com; > shawn...@kernel.org; Leo

RE: [PATCH 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property

Hi Rob, Thanks a lot for your review and ack! Regards, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2020年9月15日 9:31 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; M.h. Lian > ; devicet...@vger.kernel.org; > gustavo.

RE: [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

Hi Rob, Thanks a lot for your review and ack! Regards, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2020年9月15日 9:31 > To: Z.q. Hou > Cc: bhelg...@google.com; linux-kernel@vger.kernel.org; > shawn...@kernel.org; Leo Li ; > linux-...@vger.kernel.or

RE: [PATCH 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL

Hi Rob, Thanks a lot for your review! Regards, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2020年9月15日 9:16 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelg...@google.com; > shawn.

RE: [PATCHv7 12/12] misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers

Hi Rob, Thanks a lot for your review and ack! Regards, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 2:18 > To: Z.q. Hou > Cc: bhelg...@google.com; shawn...@kernel.org; M.h. Lian > ; Leo Li ; > linuxppc-...@lists.ozlabs.org; robh...@kernel

RE: [PATCHv7 04/12] PCI: designware-ep: Modify MSI and MSIX CAP way of finding

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 2:10 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linuxppc

RE: [PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 1:58 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linuxppc

RE: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 0:48 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linuxppc

RE: [PATCH 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL

Hi Gustavo, Thanks a lot for your review and ack! Regards, Zhiqiang > -Original Message- > From: Gustavo Pimentel > Sent: 2020年9月9日 17:29 > To: Z.q. Hou ; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelg...@google.com;

RE: [PATCHv2] PCI: designware-ep: Fix the Header Type check

Hi Rob, Thanks a lot for your review! Regards, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2020年8月18日 21:52 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; PCI ; Lorenzo > Pieralisi ; Bjorn Helgaas > ; Andrew Murray > ; Jingoo Han ; > Gust

RE: [PATCH] PCI: designware-ep: Fix the Header Type check

Hi Rob, Thanks a lot for your comments! > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: 2020年8月14日 23:51 > To: Z.q. Hou > Cc: linux-kernel@vger.kernel.org; PCI ; Lorenzo > Pieralisi ; Bjorn Helgaas > ; Andrew Murray ; > Jingo

RE: [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: 2020年7月6日 18:47 > To: Xiaowei Bao > Cc: Z.q. Hou ; M.h. Lian ; > Mingkai Hu ; bhelg...@google.com; > robh...@kernel.org; shawn...@kernel.org; Leo Li ; > kis...@t

RE: [PATCH] PCI: ERR: Don't override the status returned by error_detect()

Hi Kuppuswamy, Thanks a lot for your comments and sorry for my late response! > -Original Message- > From: Kuppuswamy, Sathyanarayanan > > Sent: 2020年5月29日 12:25 > To: Z.q. Hou ; linux-...@vger.kernel.org; > linux-kernel@vger.kernel.org; rus...@russell.cc; sbobr...@li

RE: [PATCH] PCI: ERR: Don't override the status returned by error_detect()

Hi Kuppuswamy, > -Original Message- > From: Kuppuswamy, Sathyanarayanan > > Sent: 2020年5月29日 5:19 > To: Z.q. Hou ; linux-...@vger.kernel.org; > linux-kernel@vger.kernel.org; rus...@russell.cc; sbobr...@linux.ibm.com; > ooh...@gmail.com; bhelg...@google.com > Subje

RE: [PATCH v3 00/11] *** SUBJECT HERE ***

.com; > gustavo.pimen...@synopsys.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linuxppc-...@lists.ozlabs.org > Cc: a...@arndb.de; gre...@linuxfoundation.org; Z.q. Hou > ; Xiaowei Bao > Subject: [PATCH v3 00/

RE: [PATCHv2 1/4] dt-bindings: PCI: designware: Remove the num-lanes from Required properties

Hi Rob, Thanks a lot for your review! Thanks, Zhiqiang > -Original Message- > From: Rob Herring > Sent: 2019年8月28日 0:58 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synopsys.com; >

RE: [PATCH v4 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes

.@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linuxppc-...@lists.ozlabs.org; Z.q. > Hou > Cc: bhelg...@google.com; Xiaowei Bao ; Z.q. Hou > > Subject: [PATCH v4 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes > > LS1028a imple

RE: [PATCHv2 1/4] dt-bindings: PCI: designware: Remove the num-lanes from Required properties

Hi Andrew, Thanks a lot for your review! Thanks, Zhiqiang > -Original Message- > From: Andrew Murray > Sent: 2019年8月20日 17:23 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synop

[PATCHv2 4/4] arm64: dts: fsl: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang Remove the num-lanes to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word), and the PCIe link training is

[PATCHv2 1/4] dt-bindings: PCI: designware: Remove the num-lanes from Required properties

From: Hou Zhiqiang The num-lanes is not a mandatory property, e.g. on FSL Layerscape SoCs, the PCIe link training is completed automatically base on the selected SerDes protocol, it doesn't need the num-lanes to set-up the link width. It is previously in both Required and Optional properties,

[PATCHv2 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang Remove the num-lanes to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word), and the PCIe link training is

[PATCHv2 2/4] PCI: dwc: Return directly when num-lanes is not found

From: Hou Zhiqiang The num-lanes is optional, so probably it isn't added on some platforms. The subsequent programming is base on the num-lanes, hence return when it is not found. Signed-off-by: Hou Zhiqiang Reviewed-by: Andrew Murray --- V2: - No change.

[PATCHv2 0/4] Layerscape: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol. The current num-lanes indicates the max lanes PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. This

RE: [PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

Hi Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas [mailto:helg...@kernel.org] > Sent: 2019年8月20日 3:25 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synop

RE: [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from Required properties

Hi Bjorn, Thanks a lot for your comments! > -Original Message- > From: Bjorn Helgaas [mailto:helg...@kernel.org] > Sent: 2019年8月20日 3:20 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synop

RE: [PATCHv3 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes

; M.h. Lian ; Mingkai Hu ; > Z.q. Hou ; Roy Zang ; > kstew...@linuxfoundation.org; pombreda...@nexb.com; > shawn@rock-chips.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linuxppc-...@lists.ozl

[PATCHv8 3/7] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller

From: Hou Zhiqiang Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- V8: - No change. .../bindings/pci/layerscape-pcie-gen4.txt | 52 +++ MAINTAINERS | 8 +++ 2 files

[PATCHv8 2/7] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host

From: Hou Zhiqiang Make the mobiveil_host_init() function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon hot-reset. Signed-off-by: Hou Zhiqiang Reviewed-by: Subrahmanya

[PATCHv8 1/7] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver

From: Hou Zhiqiang Refactor the Mobiveil PCIe Host Bridge IP driver to make it easier to add support for both RC and EP mode driver. This patch moved the Mobiveil driver to an new directory 'drivers/pci/controller/mobiveil' and refactor it according to the RC and EP abstraction. Signed-off-by:

[PATCHv8 6/7] arm64: dts: lx2160a: Add PCIe controller DT nodes

From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V8: - No change. .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++ 1 file changed, 163 insertions(+) diff --git

[PATCHv8 5/7] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs

From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V8: - Clear the interrupt status register before enabling interrupts. - Disable

[PATCHv8 7/7] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4

From: Hou Zhiqiang Enable the PCIe Gen4 controller driver for Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V8: - No change. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig

[PATCHv8 4/7] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors

From: Hou Zhiqiang There are some 8-bit and 16-bit registers in PCIe configuration space, so add these accessors accordingly. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa --- V8: - No change. .../pci/controller/mobiveil/pcie-mobiveil.h | 20

[PATCHv8 0/7] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs

From: Hou Zhiqiang This patch set is aim to refactor the Mobiveil driver and add PCIe support for NXP Layerscape series SoCs integrated Mobiveil's PCIe Gen4 controller. This patch set depends on: http://patchwork.ozlabs.org/patch/1131624/ Hou Zhiqiang (7): PCI: mobiveil: Refactor Mobiveil

RE: [PATCH 4/4] arm64: dts: fsl: Remove num-lanes property from PCIe nodes

Hi Andrew, Thanks a lot for your review! Regards, Zhiqiang > -Original Message- > From: Andrew Murray > Sent: 2019年8月12日 16:36 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synop

RE: [PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

Hi Andrew, Thanks a lot for your review! Regards, Zhiqiang > -Original Message- > From: Andrew Murray > Sent: 2019年8月12日 16:35 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synop

RE: [PATCH 2/4] PCI: dwc: Return directly when num-lanes is not found

Hi Andrew, Thanks a lot for your review! B.R, Zhiqiang > -Original Message- > From: Andrew Murray > Sent: 2019年8月12日 16:34 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synopsys.com; >

RE: [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from Required properties

Hi Andrew, Thanks a lot for your comments! > -Original Message- > From: Andrew Murray > Sent: 2019年8月12日 16:45 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synopsys.com; > jingoo

[PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from Required properties

From: Hou Zhiqiang The num-lanes is not a mandatory property, e.g. on FSL Layerscape SoCs, the PCIe link training is completed automatically base on the selected SerDes protocol, it doesn't need the num-lanes to set-up the link width. It has been added in the Optional properties. This patch is

[PATCH 2/4] PCI: dwc: Return directly when num-lanes is not found

From: Hou Zhiqiang The num-lanes is optional, so probably it isn't added on some platforms. The subsequent programming is base on the num-lanes, hence return when it is not found. Signed-off-by: Hou Zhiqiang --- drivers/pci/controller/dwc/pcie-designware.c | 6 -- 1 file changed, 4

[PATCH 0/4] Layerscape: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol. The current num-lanes indicates the max lanes PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. This

[PATCH 4/4] arm64: dts: fsl: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word), and the PCIe link training is completed automatically base on the selected SerDes protocol, and the

[PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

From: Hou Zhiqiang On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word), and the PCIe link training is completed automatically base on the selected SerDes protocol, and the

RE: [PATCHv2 3/3] PCI: layerscape: Add LS1028a support

a...@arndb.de; gre...@linuxfoundation.org; > M.h. Lian ; Mingkai Hu ; > Z.q. Hou ; Roy Zang ; > kstew...@linuxfoundation.org; pombreda...@nexb.com; > shawn@rock-chips.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org

RE: [PATCHv6 00/28] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver

Hi Lorenzo, Thanks for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月8日 19:35 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhel

RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月4日 18:57 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelg...@google.com; robh...@

RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change

Hi Lorenzo, Thanks for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月3日 23:19 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhel

RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change

Hi Lorenzo, Thanks for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月3日 23:10 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhel

RE: [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number

Hi Lorenzo, Thanks for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月3日 22:17 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhel

RE: [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年7月3日 18:33 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月29日 1:06 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月29日 0:42 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月29日 0:02 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月28日 19:36 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

[PATCHv7 6/7] arm64: dts: lx2160a: Add PCIe controller DT nodes

From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V7: - No change. .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++ 1 file changed, 163 insertions(+) diff --git

[PATCHv7 5/7] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs

From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V7: - No change. drivers/pci/controller/mobiveil/Kconfig | 10 +

[PATCHv7 7/7] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4

From: Hou Zhiqiang Enable the PCIe Gen4 controller driver for Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V7: - No change. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig

[PATCHv7 4/7] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors

From: Hou Zhiqiang There are some 8-bit and 16-bit registers in PCIe configuration space, so add these accessors accordingly. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa --- V7: - New patch moved from the fixes series.

[PATCHv7 2/7] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host

From: Hou Zhiqiang Make the mobiveil_host_init() function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon hot-reset. Signed-off-by: Hou Zhiqiang Reviewed-by: Subrahmanya

[PATCHv7 3/7] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller

From: Hou Zhiqiang Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- V7: - No change. .../bindings/pci/layerscape-pcie-gen4.txt | 52 +++ MAINTAINERS | 8 +++ 2 files

[PATCHv7 0/7] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs

From: Hou Zhiqiang This patch set is aim to refactor the Mobiveil driver and add PCIe support for NXP Layerscape series SoCs integrated Mobiveil's PCIe Gen4 controller. This patch set depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=102378 Hou Zhiqiang (7): PCI:

[PATCHv7 1/7] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver

From: Hou Zhiqiang Refactor the Mobiveil PCIe Host Bridge IP driver to make it easier to add support for both RC and EP mode driver. This patch moved the Mobiveil driver to an new directory 'drivers/pci/controller/mobiveil' and refactor it according to the RC and EP abstraction. Signed-off-by:

RE: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors

Hi Karthikeyan, > -Original Message- > From: Karthikeyan Mitran [mailto:m.karthike...@mobiveil.co.in] > Sent: 2019年6月19日 13:29 > To: Lorenzo Pieralisi > Cc: Z.q. Hou ; linux-...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.o

RE: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月17日 17:31 > To: Z.q. Hou > Cc: bhelg...@google.com; linux-...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; robh...@

RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月17日 17:34 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelg...@google.com; robh...@

RE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月17日 17:29 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelg...@google.com; robh...@

RE: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: 2019年6月13日 0:24 > To: Z.q. Hou ; bhelg...@google.com > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kern

RE: [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: 2019年6月12日 22:35 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: 2019年6月12日 21:08 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: 2019年6月12日 21:54 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv5 16/20] PCI: mobiveil: Add link up condition check

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月12日 1:18 > To: Z.q. Hou ; bhelg...@google.com > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kern

RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI

Hi Lorenzo, Thanks a lot for your comments! > -Original Message- > From: Lorenzo Pieralisi > Sent: 2019年6月12日 1:00 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >

RE: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes

Hi Karthikeyan, Thanks a lot for your comments! > -Original Message- > From: Karthikeyan Mitran [mailto:m.karthike...@mobiveil.co.in] > Sent: 2019年6月3日 13:13 > To: Z.q. Hou > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel

[PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes

From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V6: - No change. .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++ 1 file changed, 163 insertions(+) diff --git

[PATCHv6 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs

From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V6: - Change the file name pci-layerscape-gen4.c to pcie-layerscape-gen4.c. -

[PATCHv6 6/6] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4

From: Hou Zhiqiang Enable the PCIe Gen4 controller driver for Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V6: - Change the macro name to CONFIG_PCIE_LAYERSCAPE_GEN4. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCHv6 1/6] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver

From: Hou Zhiqiang Refactor the Mobiveil PCIe Host Bridge IP driver to make it easier to add support for both RC and EP mode driver. This patch moved the Mobiveil driver to an new directory 'drivers/pci/controller/mobiveil' and refactor it according to the RC and EP abstraction. Signed-off-by:

  1   2   3   4   5   >