Re: [GIT PULL] FPGA changes for 4.10

24045c8e01fed459d1fc833: > > > > uio: pruss: add clk_disable() (2016-11-29 20:43:12 +0100) > > > > are available in the git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git > > tags/fpga-for-greg-20161129 > > Now pulled and pushed out, thanks. Thanks! Alan > > greg k-h >

Re: [GIT PULL] FPGA changes for 4.10

24045c8e01fed459d1fc833: > > > > uio: pruss: add clk_disable() (2016-11-29 20:43:12 +0100) > > > > are available in the git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git > > tags/fpga-for-greg-20161129 > > Now pulled and pushed out, thanks. Thanks! Alan > > greg k-h >

Re: [PATCH] fpga: fix sparse warnings in fpga-mgr and fpga-bridge

On Sat, 3 Dec 2016, Moritz Fischer wrote: > On Fri, Dec 2, 2016 at 1:23 PM, Dinh Nguyen wrote: > > Fix up these sparse warnings: > > > > drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not > > declared. Should it be static? > >

Re: [PATCH] fpga: fix sparse warnings in fpga-mgr and fpga-bridge

On Sat, 3 Dec 2016, Moritz Fischer wrote: > On Fri, Dec 2, 2016 at 1:23 PM, Dinh Nguyen wrote: > > Fix up these sparse warnings: > > > > drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not > > declared. Should it be static? > > drivers/fpga/fpga-bridge.c:30:12: warning:

Re: [PATCH v3 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Joshua, > Hi Alan, > > On 11/30/2016 09:45 AM, atull wrote: > > On Wed, 30 Nov 2016, Joshua Clayton wrote: > > > > Hi Clayton, > > > > I just have a few minor one line changes below. Only one > > is o

Re: [PATCH v3 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Joshua, > Hi Alan, > > On 11/30/2016 09:45 AM, atull wrote: > > On Wed, 30 Nov 2016, Joshua Clayton wrote: > > > > Hi Clayton, > > > > I just have a few minor one line changes below. Only one > > is o

Re: [PATCH v3 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Joshua, The DT bindings will need Rob Herring's ack. The bitrev.h changes will need Russell King's ack. I've made some comments on patch 3/3 but it looks good to me besides that. Once we have those other acks, please submit your v4 including fixes

Re: [PATCH v3 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Joshua, The DT bindings will need Rob Herring's ack. The bitrev.h changes will need Russell King's ack. I've made some comments on patch 3/3 but it looks good to me besides that. Once we have those other acks, please submit your v4 including fixes

Re: [PATCH v3 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Clayton, I just have a few minor one line changes below. Only one is operational, I should have caught that earlier. > cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" > interface on Altera Cyclone FPGAS. > > This is one of

Re: [PATCH v3 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Clayton, I just have a few minor one line changes below. Only one is operational, I should have caught that earlier. > cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" > interface on Altera Cyclone FPGAS. > > This is one of

Re: [PATCH 2/2] MAINTAINERS: Add myself as co-maintainer to fpga mgr framework.

On Mon, 21 Nov 2016, Moritz Fischer wrote: > Add myself as co-maintainer to fpga mgr framework. > > Signed-off-by: Moritz Fischer > Cc: Alan Tull > Cc: Greg Kroah-Hartman > Cc: linux-kernel@vger.kernel.org > Cc:

Re: [PATCH 2/2] MAINTAINERS: Add myself as co-maintainer to fpga mgr framework.

On Mon, 21 Nov 2016, Moritz Fischer wrote: > Add myself as co-maintainer to fpga mgr framework. > > Signed-off-by: Moritz Fischer > Cc: Alan Tull > Cc: Greg Kroah-Hartman > Cc: linux-kernel@vger.kernel.org > Cc: linux-f...@vger.kernel.org > --- > Hi all, > > Lately we've fallen behind a bit

Re: [PATCH v4 1/2] of: Add vendor prefix for Lattice Semiconductor

On Sat, 29 Oct 2016, Joel Holdsworth wrote: > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt > b/Documentation/devicetree/bindings/vendor-prefixes.txt > index

Re: [PATCH v4 1/2] of: Add vendor prefix for Lattice Semiconductor

On Sat, 29 Oct 2016, Joel Holdsworth wrote: > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt > b/Documentation/devicetree/bindings/vendor-prefixes.txt > index

Re: [PATCH v8 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager

On Mon, 14 Nov 2016, Rob Herring wrote: > On Sun, Nov 06, 2016 at 07:49:21PM -0700, Joel Holdsworth wrote: > > This adds documentation of the device tree bindings of the Lattice iCE40 > > FPGA driver for the FPGA manager framework. > > > > Signed-off-by: Joel Holdsworth

Re: [PATCH v8 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager

On Mon, 14 Nov 2016, Rob Herring wrote: > On Sun, Nov 06, 2016 at 07:49:21PM -0700, Joel Holdsworth wrote: > > This adds documentation of the device tree bindings of the Lattice iCE40 > > FPGA driver for the FPGA manager framework. > > > > Signed-off-by: Joel Holdsworth > > --- > >

Re: [patch] ARM: socfpga: checking the wrong variable

On Tue, 15 Nov 2016, Moritz Fischer wrote: > Hi Dan, > On Tue, Nov 15, 2016 at 1:54 AM, Dan Carpenter > wrote: > > This is a cut and paste bug. We had intended to check "sysmgr". > > > > Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support") > >

Re: [patch] ARM: socfpga: checking the wrong variable

On Tue, 15 Nov 2016, Moritz Fischer wrote: > Hi Dan, > On Tue, Nov 15, 2016 at 1:54 AM, Dan Carpenter > wrote: > > This is a cut and paste bug. We had intended to check "sysmgr". > > > > Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support") > > Signed-off-by: Dan Carpenter >

Re: [PATCH 3/4] fpga mgr: zynq: Add support for encrypted bitstreams

On Mon, 7 Nov 2016, Moritz Fischer wrote: Hi Moritz, This looks good. Probably the socfpga changes could get folded into this patch (was patch 4/4) unless you thought of a reason not to (after that patch is changed to see if the MSEL bits are set to enable decrypt). There also could be a

Re: [PATCH 3/4] fpga mgr: zynq: Add support for encrypted bitstreams

On Mon, 7 Nov 2016, Moritz Fischer wrote: Hi Moritz, This looks good. Probably the socfpga changes could get folded into this patch (was patch 4/4) unless you thought of a reason not to (after that patch is changed to see if the MSEL bits are set to enable decrypt). There also could be a

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 14 Nov 2016, Moritz Fischer wrote: Hi Moritz, > Hi Alan, > > On Mon, Nov 14, 2016 at 6:06 AM, atull <at...@opensource.altera.com> wrote: > > On Mon, 7 Nov 2016, Moritz Fischer wrote: > > > >> Add FPGA capabilities as a way to express the capab

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 14 Nov 2016, Moritz Fischer wrote: Hi Moritz, > Hi Alan, > > On Mon, Nov 14, 2016 at 6:06 AM, atull wrote: > > On Mon, 7 Nov 2016, Moritz Fischer wrote: > > > >> Add FPGA capabilities as a way to express the capabilities > >> of a given FPGA mana

Re: [PATCH 2/4] fpga mgr: Expose FPGA capabilities to userland via sysfs

On Mon, 7 Nov 2016, Moritz Fischer wrote: Hi Moritz, One nit below. Otherwise, Acked-by: Alan Tull Alan > Expose FPGA capabilities to userland via sysfs. > > Add Documentation for currently supported capabilities > that get exported via sysfs. > >

Re: [PATCH 2/4] fpga mgr: Expose FPGA capabilities to userland via sysfs

On Mon, 7 Nov 2016, Moritz Fischer wrote: Hi Moritz, One nit below. Otherwise, Acked-by: Alan Tull Alan > Expose FPGA capabilities to userland via sysfs. > > Add Documentation for currently supported capabilities > that get exported via sysfs. > > Signed-off-by: Moritz Fischer > Cc:

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Add FPGA capabilities as a way to express the capabilities > of a given FPGA manager. > > Removes code duplication by comparing the low-level driver's > capabilities at the framework level rather than having each driver > check for supported operations

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Add FPGA capabilities as a way to express the capabilities > of a given FPGA manager. > > Removes code duplication by comparing the low-level driver's > capabilities at the framework level rather than having each driver > check for supported operations

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Add FPGA capabilities as a way to express the capabilities > of a given FPGA manager. > > Removes code duplication by comparing the low-level driver's > capabilities at the framework level rather than having each driver > check for supported operations

Re: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Add FPGA capabilities as a way to express the capabilities > of a given FPGA manager. > > Removes code duplication by comparing the low-level driver's > capabilities at the framework level rather than having each driver > check for supported operations

Re: [PATCH 4/4] fpga mgr: socfpga: Expose support for encrypted bitstreams

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Expose support for on the fly decryption of bitstreams. > This needs no additional work or configuration, > so just expose the new capability. Hi Moritz, When we talked about this, I was thinking about the arria10 support which I'd done more recently.

Re: [PATCH 4/4] fpga mgr: socfpga: Expose support for encrypted bitstreams

On Mon, 7 Nov 2016, Moritz Fischer wrote: > Expose support for on the fly decryption of bitstreams. > This needs no additional work or configuration, > so just expose the new capability. Hi Moritz, When we talked about this, I was thinking about the arria10 support which I'd done more recently.

Re: [[PATCH repost v21] 01/11] of/overlay: add of overlay notifications

On Thu, 10 Nov 2016, Greg Kroah-Hartman wrote: > On Tue, Nov 01, 2016 at 02:14:22PM -0500, Alan Tull wrote: > > This patch add of overlay notifications. > > Your crazy way of doing [ ] in the subject messed up git, please don't > do that... > > Just do: > [PATCH repost v21 01/11] >

Re: [[PATCH repost v21] 01/11] of/overlay: add of overlay notifications

On Thu, 10 Nov 2016, Greg Kroah-Hartman wrote: > On Tue, Nov 01, 2016 at 02:14:22PM -0500, Alan Tull wrote: > > This patch add of overlay notifications. > > Your crazy way of doing [ ] in the subject messed up git, please don't > do that... > > Just do: > [PATCH repost v21 01/11] >

Re: [PATCH v7 3/3] fpga: Add support for Lattice iCE40 FPGAs

On Fri, 4 Nov 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [PATCH v7 3/3] fpga: Add support for Lattice iCE40 FPGAs

On Fri, 4 Nov 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [PATCH v7 3/3] fpga: Add support for Lattice iCE40 FPGAs

On Fri, 4 Nov 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [PATCH v7 3/3] fpga: Add support for Lattice iCE40 FPGAs

On Fri, 4 Nov 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [RFC] fpga: Pull checks for supported operations into framework

On Mon, 31 Oct 2016, Moritz Fischer wrote: > Found a couple of issues, will resubmit after cleaning up. Feel free to add > general feedback on the idea anyways in the meantime. Sorry for double post. Hi Moritz, This looks good and useful to me. One comment below. > > On Sun, Oct 30, 2016 at

Re: [RFC] fpga: Pull checks for supported operations into framework

On Mon, 31 Oct 2016, Moritz Fischer wrote: > Found a couple of issues, will resubmit after cleaning up. Feel free to add > general feedback on the idea anyways in the meantime. Sorry for double post. Hi Moritz, This looks good and useful to me. One comment below. > > On Sun, Oct 30, 2016 at

Re: [v2 2/2] fpga: Add support for Lattice iCE40 FPGAs

On Tue, 25 Oct 2016, Joel Holdsworth wrote: > > > Hi Joel, > > > > Thanks for submitting your driver! > > > > I didn't see any huge problems, just minor things below... > > > > Alan > > > > Hi Alan, Thanks for your feedback. I've implemented all your suggestions and > I'll resubmit. > > I

Re: [v2 2/2] fpga: Add support for Lattice iCE40 FPGAs

On Tue, 25 Oct 2016, Joel Holdsworth wrote: > > > Hi Joel, > > > > Thanks for submitting your driver! > > > > I didn't see any huge problems, just minor things below... > > > > Alan > > > > Hi Alan, Thanks for your feedback. I've implemented all your suggestions and > I'll resubmit. > > I

Re: [v2 2/2] fpga: Add support for Lattice iCE40 FPGAs

On Mon, 24 Oct 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [v2 2/2] fpga: Add support for Lattice iCE40 FPGAs

On Mon, 24 Oct 2016, Joel Holdsworth wrote: > The Lattice iCE40 is a family of FPGAs with a minimalistic architecture > and very regular structure, designed for low-cost, high-volume consumer > and system applications. > > This patch adds support to the FPGA manager for configuring the SRAM of >

Re: [PATCH v20 10/10] fpga-manager: Add Socfpga Arria10 support

On Tue, 18 Oct 2016, Moritz Fischer wrote: > On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote: > > Add low level driver to support reprogramming FPGAs for Altera > > SoCFPGA Arria10. > > > > Signed-off-by: Alan Tull > > Reviewed-by: Moritz Fischer

Re: [PATCH v20 10/10] fpga-manager: Add Socfpga Arria10 support

On Tue, 18 Oct 2016, Moritz Fischer wrote: > On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote: > > Add low level driver to support reprogramming FPGAs for Altera > > SoCFPGA Arria10. > > > > Signed-off-by: Alan Tull > > Reviewed-by: Moritz Fischer > > + > > +MODULE_AUTHOR("Alan Tull

Re: [PATCH v20 03/10] add bindings document for altera freeze bridge

On Tue, 18 Oct 2016, Rob Herring wrote: > On Mon, Oct 17, 2016 at 11:09:34AM -0500, Alan Tull wrote: > > Add bindings document for the Altera Freeze Bridge. A Freeze > > Bridge is used to gate traffic to/from a region of a FPGA > > such that that region can be reprogrammed. The Freeze Bridge >

Re: [PATCH v20 03/10] add bindings document for altera freeze bridge

On Tue, 18 Oct 2016, Rob Herring wrote: > On Mon, Oct 17, 2016 at 11:09:34AM -0500, Alan Tull wrote: > > Add bindings document for the Altera Freeze Bridge. A Freeze > > Bridge is used to gate traffic to/from a region of a FPGA > > such that that region can be reprogrammed. The Freeze Bridge >

Re: [PATCH v20 02/10] doc: fpga-mgr: add fpga image info to api

On Mon, 17 Oct 2016, Moritz Fischer wrote: > Hi Alan, > > couple of nits inline and some comments on ordering the patches ;-) > > On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull > wrote: > > This patch adds a minor change in the FPGA Mangager API > >

Re: [PATCH v20 02/10] doc: fpga-mgr: add fpga image info to api

On Mon, 17 Oct 2016, Moritz Fischer wrote: > Hi Alan, > > couple of nits inline and some comments on ordering the patches ;-) > > On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull > wrote: > > This patch adds a minor change in the FPGA Mangager API > > s/Mangager/Manager/ Yup! > > > to hold

Re: [PATCH v20 06/10] fpga: add fpga bridge framework

On Mon, 17 Oct 2016, Alan Tull wrote: > +/** > + * of_fpga_bridge_get - get an exclusive reference to a fpga bridge > + * > + * @np: node pointer of a FPGA bridge > + * @info: fpga image specific information > + * > + * Return fpga_bridge struct if successful. > + * Return -EBUSY if someone

Re: [PATCH v20 06/10] fpga: add fpga bridge framework

On Mon, 17 Oct 2016, Alan Tull wrote: > +/** > + * of_fpga_bridge_get - get an exclusive reference to a fpga bridge > + * > + * @np: node pointer of a FPGA bridge > + * @info: fpga image specific information > + * > + * Return fpga_bridge struct if successful. > + * Return -EBUSY if someone

Re: [PATCH v19 01/12] fpga: add bindings document for fpga region

On Sat, 8 Oct 2016, Rob Herring wrote: > On Wed, Sep 28, 2016 at 01:21:49PM -0500, Alan Tull wrote: > > New bindings document for FPGA Region to support programming > > FPGA's under Device Tree control > > > > Signed-off-by: Alan Tull > > Signed-off-by: Moritz

Re: [PATCH v19 01/12] fpga: add bindings document for fpga region

On Sat, 8 Oct 2016, Rob Herring wrote: > On Wed, Sep 28, 2016 at 01:21:49PM -0500, Alan Tull wrote: > > New bindings document for FPGA Region to support programming > > FPGA's under Device Tree control > > > > Signed-off-by: Alan Tull > > Signed-off-by: Moritz Fischer > > --- > > v9: initial

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Thu, 6 Oct 2016, Joshua Clayton wrote: > cyclonespi loads fpga firmware over spi, using the "passive serial" > interface on Altera Cyclone FPGAS. > > one of the simpler ways to set up an fpga at runtime. > The signal interface is close to unidirectional spi with lsb first. > > Signed-off-by:

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Thu, 6 Oct 2016, Joshua Clayton wrote: > cyclonespi loads fpga firmware over spi, using the "passive serial" > interface on Altera Cyclone FPGAS. > > one of the simpler ways to set up an fpga at runtime. > The signal interface is close to unidirectional spi with lsb first. > > Signed-off-by:

Re: [PATCH v19 03/12] add bindings document for altera freeze bridge

On Sat, 8 Oct 2016, Rob Herring wrote: > On Wed, Sep 28, 2016 at 01:21:51PM -0500, Alan Tull wrote: > > Add bindings document for the Altera Freeze Bridge. A Freeze > > Bridge is used to gate traffic to/from a region of a FPGA > > such that that region can be reprogrammed. The Freeze Bridge > >

Re: [PATCH v19 03/12] add bindings document for altera freeze bridge

On Sat, 8 Oct 2016, Rob Herring wrote: > On Wed, Sep 28, 2016 at 01:21:51PM -0500, Alan Tull wrote: > > Add bindings document for the Altera Freeze Bridge. A Freeze > > Bridge is used to gate traffic to/from a region of a FPGA > > such that that region can be reprogrammed. The Freeze Bridge > >

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Fri, 7 Oct 2016, Moritz Fischer wrote: > Hi Alan, > > On Fri, Oct 7, 2016 at 11:21 AM, atull <at...@opensource.altera.com> wrote: > > > Moritz, Can you remind me what that issue was there (or point me to > > that email, I can't find it)? I don't think I had a

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Fri, 7 Oct 2016, Moritz Fischer wrote: > Hi Alan, > > On Fri, Oct 7, 2016 at 11:21 AM, atull wrote: > > > Moritz, Can you remind me what that issue was there (or point me to > > that email, I can't find it)? I don't think I had a problem with that > > in

Re: [PATCH 2/3] doc: dt: add cyclone-spi binding document

On Fri, 7 Oct 2016, Moritz Fischer wrote: > > +referred to as "passive serial". > > +The passive serial link is not technically spi, and might require extra > > +circuits in order to play nicely with other spi slaves on the same bus. > > + > > +See

Re: [PATCH 2/3] doc: dt: add cyclone-spi binding document

On Fri, 7 Oct 2016, Moritz Fischer wrote: > > +referred to as "passive serial". > > +The passive serial link is not technically spi, and might require extra > > +circuits in order to play nicely with other spi slaves on the same bus. > > + > > +See

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Fri, 7 Oct 2016, Moritz Fischer wrote: > > +static inline u32 revbit8x4(u32 n) > > +{ > > + n = ((n & 0xF0F0F0F0UL) >> 4) | ((n & 0x0F0F0F0FUL) << 4); > > + n = ((n & 0xUL) >> 2) | ((n & 0xUL) << 2); > > + n = ((n & 0xUL) >> 1) | ((n & 0xUL) <<

Re: [PATCH 1/3] fpga manager: Add cyclonespi driver for Altera fpgas

On Fri, 7 Oct 2016, Moritz Fischer wrote: > > +static inline u32 revbit8x4(u32 n) > > +{ > > + n = ((n & 0xF0F0F0F0UL) >> 4) | ((n & 0x0F0F0F0FUL) << 4); > > + n = ((n & 0xUL) >> 2) | ((n & 0xUL) << 2); > > + n = ((n & 0xUL) >> 1) | ((n & 0xUL) <<

Re: [PATCH v19 12/12] fpga-manager: Add Socfpga Arria10 support

On Thu, 29 Sep 2016, Moritz Fischer wrote: > Hi Alan, > > On Wed, Sep 28, 2016 at 11:22 AM, Alan Tull > wrote: > > > +static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv, > > + u32 count) > > +{ > > +

Re: [PATCH v19 12/12] fpga-manager: Add Socfpga Arria10 support

On Thu, 29 Sep 2016, Moritz Fischer wrote: > Hi Alan, > > On Wed, Sep 28, 2016 at 11:22 AM, Alan Tull > wrote: > > > +static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv, > > + u32 count) > > +{ > > + u32 val; > > +

Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support

On Tue, 9 Aug 2016, Paul Gortmaker wrote: > [Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support] On 08/08/2016 > (Mon 13:44) Moritz Fischer wrote: > > > Hi Alan, > > > > On Mon, Aug 8, 2016 at 12:18 PM, atull <at...@opensource.altera.com> wrote: >

Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support

On Tue, 9 Aug 2016, Paul Gortmaker wrote: > [Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support] On 08/08/2016 > (Mon 13:44) Moritz Fischer wrote: > > > Hi Alan, > > > > On Mon, Aug 8, 2016 at 12:18 PM, atull wrote: > > > > >> Pl

Re: [PATCH v2] fpga manager: Add hardware dependency to Zynq driver

On Thu, 8 Sep 2016, Jean Delvare wrote: Hi Greg, Can you take in this patch? Thanks, Alan > The Zynq FPGA manager driver serves no purpose on other architectures > so hide it unless build-testing. > > Signed-off-by: Jean Delvare > Acked-by: Moritz Fischer

Re: [PATCH v2] fpga manager: Add hardware dependency to Zynq driver

On Thu, 8 Sep 2016, Jean Delvare wrote: Hi Greg, Can you take in this patch? Thanks, Alan > The Zynq FPGA manager driver serves no purpose on other architectures > so hide it unless build-testing. > > Signed-off-by: Jean Delvare > Acked-by: Moritz Fischer > Acked-by: Alan Tull > Acked-by:

Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 14 Jul 2016, Paul Gortmaker wrote: > On Tue, Jul 12, 2016 at 3:36 PM, Alan Tull > wrote: > > Supports Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Allows enabling/disabling the bridges through the FPGA >

Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 14 Jul 2016, Paul Gortmaker wrote: > On Tue, Jul 12, 2016 at 3:36 PM, Alan Tull > wrote: > > Supports Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Allows enabling/disabling the bridges through the FPGA > > Bridge Framework API

Re: [PATCH v18 2/6] ARM: socfpga: add bindings document for fpga bridge drivers

On Mon, 1 Aug 2016, Rob Herring wrote: > On Tue, Jul 12, 2016 at 02:36:41PM -0500, Alan Tull wrote: > > Add bindings documentation for Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Signed-off-by: Alan Tull > >

Re: [PATCH v18 2/6] ARM: socfpga: add bindings document for fpga bridge drivers

On Mon, 1 Aug 2016, Rob Herring wrote: > On Tue, Jul 12, 2016 at 02:36:41PM -0500, Alan Tull wrote: > > Add bindings documentation for Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Signed-off-by: Alan Tull > > Signed-off-by: Matthew Gerlach

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 28 Jul 2016, Trent Piepho wrote: > On Thu, 2016-07-28 at 10:21 -0500, atull wrote: > > > > > > > > This isn't going work if more than one bridge is used. Each bridge has > > > > its own priv and thus priv->l3_remap_value. Each bridge's priv w

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 28 Jul 2016, Trent Piepho wrote: > On Thu, 2016-07-28 at 10:21 -0500, atull wrote: > > > > > > > > This isn't going work if more than one bridge is used. Each bridge has > > > > its own priv and thus priv->l3_remap_value. Each bridge's priv w

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 28 Jul 2016, Andrea Galbusera wrote: > On Fri, Jun 10, 2016 at 4:18 AM, Trent Piepho wrote: > > On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote: > >> Supports Altera SOCFPGA bridges: > >> * fpga2sdram > >> * fpga2hps > >> * hps2fpga > >> *

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Thu, 28 Jul 2016, Andrea Galbusera wrote: > On Fri, Jun 10, 2016 at 4:18 AM, Trent Piepho wrote: > > On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote: > >> Supports Altera SOCFPGA bridges: > >> * fpga2sdram > >> * fpga2hps > >> * hps2fpga > >> * lwhps2fpga > >> > >>

Re: [PATCH] fpga: zynq: Add hardware dependencies

On Sun, 17 Jul 2016, Moritz Fischer wrote: > On Thu, Jul 7, 2016 at 1:07 AM, Jean Delvare wrote: > > The zynq-fpga driver is specific to its architecture, so do not > > propose it on other architectures, unless build-testing. > > > > Signed-off-by: Jean Delvare

Re: [PATCH] fpga: zynq: Add hardware dependencies

On Sun, 17 Jul 2016, Moritz Fischer wrote: > On Thu, Jul 7, 2016 at 1:07 AM, Jean Delvare wrote: > > The zynq-fpga driver is specific to its architecture, so do not > > propose it on other architectures, unless build-testing. > > > > Signed-off-by: Jean Delvare > > Cc: Moritz Fischer > > Cc:

Re: [PATCH 1/2] ARM: socfpga: add bindings doc for arria10 fpga manager

On Sun, 17 Jul 2016, Moritz Fischer wrote: > Acked-By: Moritz Fischer Thanks Moritz! Alan > > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > wrote: > > Add a device tree bindings document for the SoCFPGA Arria10 > > FPGA Manager driver.

Re: [PATCH 1/2] ARM: socfpga: add bindings doc for arria10 fpga manager

On Sun, 17 Jul 2016, Moritz Fischer wrote: > Acked-By: Moritz Fischer Thanks Moritz! Alan > > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > wrote: > > Add a device tree bindings document for the SoCFPGA Arria10 > > FPGA Manager driver. > > > > Signed-off-by: Alan Tull > > --- > >

Re: [PATCH 1/2] ARM: socfpga: add bindings doc for arria10 fpga manager

On Sat, 16 Jul 2016, Rob Herring wrote: > On Tue, Jul 12, 2016 at 02:07:08PM -0500, Alan Tull wrote: > > Add a device tree bindings document for the SoCFPGA Arria10 > > FPGA Manager driver. > > > > Signed-off-by: Alan Tull > > --- > >

Re: [PATCH 1/2] ARM: socfpga: add bindings doc for arria10 fpga manager

On Sat, 16 Jul 2016, Rob Herring wrote: > On Tue, Jul 12, 2016 at 02:07:08PM -0500, Alan Tull wrote: > > Add a device tree bindings document for the SoCFPGA Arria10 > > FPGA Manager driver. > > > > Signed-off-by: Alan Tull > > --- > > .../bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 19

Re: [PATCH 2/2] fpga-manager: Add Socfpga Arria10 support

On Tue, 12 Jul 2016, Moritz Fischer wrote: > Hi Alan, > > couple of nits inline below. > Hi Moritz! Thanks for your review! > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > wrote: > > > +static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr, u32

Re: [PATCH 2/2] fpga-manager: Add Socfpga Arria10 support

On Tue, 12 Jul 2016, Moritz Fischer wrote: > Hi Alan, > > couple of nits inline below. > Hi Moritz! Thanks for your review! > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > wrote: > > > +static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr, u32 > > flags) > > +{ > > +

Re: [PATCH 2/2] fpga-manager: Add Socfpga Arria10 support

On Tue, 12 Jul 2016, Russell King - ARM Linux wrote: > On Tue, Jul 12, 2016 at 02:31:05PM -0700, Moritz Fischer wrote: > > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > > wrote: > > > + priv->clk = devm_clk_get(dev, NULL); > > > + if (IS_ERR(priv->clk))

Re: [PATCH 2/2] fpga-manager: Add Socfpga Arria10 support

On Tue, 12 Jul 2016, Russell King - ARM Linux wrote: > On Tue, Jul 12, 2016 at 02:31:05PM -0700, Moritz Fischer wrote: > > On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull > > wrote: > > > + priv->clk = devm_clk_get(dev, NULL); > > > + if (IS_ERR(priv->clk)) { > > > +

Re: [PATCH v18 0/6] Device Tree support for FPGA Programming

On Tue, 12 Jul 2016, Alan Tull wrote: > v18 has very minimal changes to address comments about the device > tree bindings and device tree examples in the bindings document. > > The diffstat from v17 is: > 4 files changed, 11 insertions(+), 18 deletions(-) > If there are more changes, it would

Re: [PATCH v18 0/6] Device Tree support for FPGA Programming

On Tue, 12 Jul 2016, Alan Tull wrote: > v18 has very minimal changes to address comments about the device > tree bindings and device tree examples in the bindings document. > > The diffstat from v17 is: > 4 files changed, 11 insertions(+), 18 deletions(-) > If there are more changes, it would

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Fri, 10 Jun 2016, Trent Piepho wrote: > On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote: > > Supports Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Allows enabling/disabling the bridges through the FPGA > > Bridge

Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

On Fri, 10 Jun 2016, Trent Piepho wrote: > On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote: > > Supports Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Allows enabling/disabling the bridges through the FPGA > > Bridge

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > If NO_DMA=y: > > ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! > > Add a dependency on HAS_DMA to fix this. > > Signed-off-by: Geert Uytterhoeven > Reviewed-by: Moritz Fischer

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > If NO_DMA=y: > > ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! > > Add a dependency on HAS_DMA to fix this. > > Signed-off-by: Geert Uytterhoeven > Reviewed-by: Moritz Fischer Acked-by: Alan Tull Thanks! Alan > --- > v2: >

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Mon, 6 Jun 2016, Moritz Fischer wrote: > Hi Alan, Geert > > On Mon, Jun 6, 2016 at 11:02 AM, atull <at...@opensource.altera.com> wrote: > > On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > > > >> If NO_DMA=y: > >> > >> ERRO

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Mon, 6 Jun 2016, Moritz Fischer wrote: > Hi Alan, Geert > > On Mon, Jun 6, 2016 at 11:02 AM, atull wrote: > > On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > > > >> If NO_DMA=y: > >> > >> ERROR: "bad_dma_ops" [drivers/fpga/zynq

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > If NO_DMA=y: > > ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! > > Add a dependency on HAS_DMA to fix this. > > Signed-off-by: Geert Uytterhoeven > Reviewed-by: Moritz Fischer >

Re: [PATCH v2] fpga: FPGA_MGR_ZYNQ_FPGA should depend on HAS_DMA

On Sun, 5 Jun 2016, Geert Uytterhoeven wrote: > If NO_DMA=y: > > ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! > > Add a dependency on HAS_DMA to fix this. > > Signed-off-by: Geert Uytterhoeven > Reviewed-by: Moritz Fischer > --- > v2: > - Add Reviewed-by, > - Updated

Re: [PATCH 17/54] MAINTAINERS: Add file patterns for fpga device tree bindings

On Sun, 22 May 2016, Geert Uytterhoeven wrote: > Submitters of device tree binding documentation may forget to CC > the subsystem maintainer if this is missing. > > Signed-off-by: Geert Uytterhoeven > Cc: Alan Tull > Cc: Moritz Fischer

Re: [PATCH 17/54] MAINTAINERS: Add file patterns for fpga device tree bindings

On Sun, 22 May 2016, Geert Uytterhoeven wrote: > Submitters of device tree binding documentation may forget to CC > the subsystem maintainer if this is missing. > > Signed-off-by: Geert Uytterhoeven > Cc: Alan Tull > Cc: Moritz Fischer > --- > Please apply this patch directly if you want to

Re: [PATCH v3] of/overlay: add of overlay notifications

On Tue, 19 Apr 2016, Rob Herring wrote: > On Thu, Mar 3, 2016 at 9:10 AM, Alan Tull wrote: > > This patch add of overlay notifications. > > > > When DT overlays are being added, some drivers/subsystems > > need to see device tree overlays before the changes go into >

Re: [PATCH v3] of/overlay: add of overlay notifications

On Tue, 19 Apr 2016, Rob Herring wrote: > On Thu, Mar 3, 2016 at 9:10 AM, Alan Tull wrote: > > This patch add of overlay notifications. > > > > When DT overlays are being added, some drivers/subsystems > > need to see device tree overlays before the changes go into > > the live tree. > > > >

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