[RESEND PATCH] usb: dwc2: Add reset control to dwc2

From: Dinh Nguyen Allow for platforms that have a reset controller driver in place to bring the USB IP out of reset. Signed-off-by: Dinh Nguyen Acked-by: John Youn Tested-by: Stefan Wahren

[RESEND PATCH] usb: dwc2: Add reset control to dwc2

From: Dinh Nguyen Allow for platforms that have a reset controller driver in place to bring the USB IP out of reset. Signed-off-by: Dinh Nguyen Acked-by: John Youn Tested-by: Stefan Wahren Acked-by: Felipe Balbi --- v7: Use devm_reset_control_get_optional() v6: fix 80 line checkpatch

[PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update

[PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call

[PATCH] Doc: Micrel-ksz90x1.txt: Update the Micrel phy documentation for ksz9031

From: Dinh Nguyen Update the Micrel phy documentation for the KSZ9031 PHY to represent how the actual values are calculated from the code. Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/net/micrel-ksz90x1.txt | 73 ++ 1 file changed, 73 insertions(+) diff

[PATCH] Doc: Micrel-ksz90x1.txt: Update the Micrel phy documentation for ksz9031

From: Dinh Nguyen Update the Micrel phy documentation for the KSZ9031 PHY to represent how the actual values are calculated from the code. Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/net/micrel-ksz90x1.txt | 73

[PATCH] arm: socfpga_defconfig: enable USB dual-role and cleanup

From: Dinh Nguyen Enable USB OTG dual-role and a bit of clean up by using make savedefconfig. Signed-off-by: Dinh Nguyen --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/socfpga_defconfig

[PATCH] arm: socfpga_defconfig: enable USB dual-role and cleanup

From: Dinh Nguyen Enable USB OTG dual-role and a bit of clean up by using make savedefconfig. Signed-off-by: Dinh Nguyen --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff

[PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. The SDRAM ECC is a separate Kconfig option because: 1) the SDRAM

[PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. The SDRAM ECC is a separate Kconfig option

[PATCH] EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN

From: Dinh Nguyen The bootloader may or may not enable the ECC_CORR_EN bit. By not enabling ECC_CORR_EN, when error happens, it is the user's responsibility to perform a full SDRAM scrub. Remove the check for ECC_CORR_EN. Signed-off-by: Dinh Nguyen --- drivers/edac/altera_edac.h | 3 +-- 1

[PATCH] EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN

From: Dinh Nguyen The bootloader may or may not enable the ECC_CORR_EN bit. By not enabling ECC_CORR_EN, when error happens, it is the user's responsibility to perform a full SDRAM scrub. Remove the check for ECC_CORR_EN. Signed-off-by: Dinh Nguyen

[PATCHv4] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v4: Add a non-zero ranges property for /soc node v3: change #address-cells and #size-cells to <2> change the GIC address to 0xfffc1000 update the GIC virtual CPU reg length to

[PATCHv4] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v4: Add a non-zero ranges property for /soc node v3: change #address-cells and #size-cells to <2> change the GIC

[PATCv3] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v3: change #address-cells and #size-cells to <2> change the GIC address to 0xfffc1000 update the GIC virtual CPU reg length to 0x2000 v2: use interrupt-affinity for pmu node ---

[PATCv3] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v3: change #address-cells and #size-cells to 2 change the GIC address to 0xfffc1000 update the GIC virtual CPU reg

[PATCHv2] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v2: use interrupt-affinity for pmu node --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 +

[PATCHv2] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: use interrupt-affinity for pmu node --- arch/arm64/Kconfig | 5 +

[PATCH] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/altera/Makefile| 5 +

[PATCH] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 +

[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager that is used for bringing

[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen v2: For the reset driver, assume a modrst-offset of 0x10 in order to support legacy boards that do have the property.. v1: This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on

[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++ 1 file changed, 110

[PATCHv2 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

From: Dinh Nguyen The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++

[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index

[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/dt-bindings/reset/altr,rst-mgr-a10.h |

[PATCHv2 2/4] ARM: socfpga: dts: add altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com The altr,modrst-offset property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager

[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com v2: For the reset driver, assume a modrst-offset of 0x10 in order to support legacy boards that do have the property.. v1: This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very

[PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager that is used for bringing

[PATCH 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

From: Dinh Nguyen The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++

[PATCH 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index

[PATCH 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen Hi, This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5, thus I think it's best to try to re-use the same reset driver. The biggest difference between the reset manager on

[PATCH 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++ 1 file changed, 110

[PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager

[PATCH 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/dt-bindings/reset/altr,rst-mgr-a10.h |

[PATCH 2/4] ARM: socfpga: dts: add altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com The altr,modrst-offset property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCH 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5, thus I think it's best to try to re-use the same reset driver. The biggest difference

[PATCH 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen --- v2: remove

[PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen dingu...@opensource.altera.com The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock.

[PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen ---

[PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen dingu...@opensource.altera.com The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock.

[PATCH] ARM: socfpga: add reset for the Arria 10 platform

From: Dinh Nguyen Since the Arria10's reset register offset is different from the Cyclone/Arria 5, it's best to add a new DT_MACHINE_START() for the Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/core.h| 1 + arch/arm/mach-socfpga/socfpga.c | 26 ++

[PATCH] ARM: socfpga: add reset for the Arria 10 platform

From: Dinh Nguyen dingu...@opensource.altera.com Since the Arria10's reset register offset is different from the Cyclone/Arria 5, it's best to add a new DT_MACHINE_START() for the Arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/mach-socfpga/core.h| 1 +

[PATCHv2 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Tero Kristo --- drivers/clk/ti/apll.c |4 +--- drivers/clk/ti/composite.c |4 +--- drivers/clk/ti/dpll.c |4 +--- drivers/clk/ti/fapll.c |3 +--

[PATCHv2 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Hello, This is v2 of the patchset that makes use of of_clk_parent_fill helper function on various platforms. Thanks, Dinh Nguyen (6): clk: at91: make use of of_clk_parent_fill helper function clk: qoriq: make use of of_clk_parent_fill helper function clk: keystone:

[PATCHv2 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Boris Brezillon --- drivers/clk/at91/clk-main.c |7 +-- drivers/clk/at91/clk-master.c |7 +-- drivers/clk/at91/clk-programmable.c |7 +--

[PATCHv2 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Tested-by Gabriel Fernandez Cc: Peter Griffin --- drivers/clk/st/clk-flexgen.c |6 ++ drivers/clk/st/clkgen-mux.c |7 ++- 2 files changed, 4 insertions(+), 9

[PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Maxime Ripard Cc: "Emilio López" --- v2: Add if (of_clk_parent_fill(node, parents, 2) != 2) to clk-a20-gmac.c --- drivers/clk/sunxi/clk-a20-gmac.c|4 +---

[PATCHv2 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Acked-by: Santosh Shilimkar --- drivers/clk/keystone/pll.c |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/keystone/pll.c

[PATCHv2 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen --- drivers/clk/clk-qoriq.c |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index cda90a9..d3f4570 100644

[PATCHv2 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Tero Kristo t-kri...@ti.com --- drivers/clk/ti/apll.c |4 +--- drivers/clk/ti/composite.c |4 +---

[PATCHv2 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Hello, This is v2 of the patchset that makes use of of_clk_parent_fill helper function on various platforms. Thanks, Dinh Nguyen (6): clk: at91: make use of of_clk_parent_fill helper function clk: qoriq: make use of of_clk_parent_fill helper

[PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Maxime Ripard maxime.rip...@free-electrons.com Cc: Emilio López emi...@elopez.com.ar --- v2: Add if

[PATCHv2 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Boris Brezillon boris.brezil...@free-electrons.com --- drivers/clk/at91/clk-main.c |7 +--

[PATCHv2 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Santosh Shilimkar ssant...@kernel.org --- drivers/clk/keystone/pll.c |3 +-- 1 file changed, 1 insertion(+),

[PATCHv2 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Tested-by Gabriel Fernandez gabriel.fernan...@st.com Cc: Peter Griffin peter.grif...@linaro.org ---

[PATCHv2 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- drivers/clk/clk-qoriq.c |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

[PATCH 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Santosh Shilimkar --- drivers/clk/keystone/pll.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c

[PATCH 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Peter Griffin Cc: Gabriel FERNANDEZ --- drivers/clk/st/clk-flexgen.c | 6 ++ drivers/clk/st/clkgen-mux.c | 7 ++- 2 files changed, 4 insertions(+), 9 deletions(-) diff

[PATCH 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Tero Kristo --- drivers/clk/ti/apll.c | 4 +--- drivers/clk/ti/composite.c | 4 +--- drivers/clk/ti/dpll.c | 4 +--- drivers/clk/ti/fapll.c | 3 +--

[PATCH 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Boris Brezillon --- drivers/clk/at91/clk-main.c | 7 +-- drivers/clk/at91/clk-master.c | 7 +-- drivers/clk/at91/clk-programmable.c | 7 +--

[PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Maxime Ripard Cc: "Emilio López" --- drivers/clk/sunxi/clk-a20-gmac.c| 3 +-- drivers/clk/sunxi/clk-factors.c | 4 +--- drivers/clk/sunxi/clk-sun6i-ar100.c | 3 +--

[PATCH 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen --- drivers/clk/clk-qoriq.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index cda90a9..d3f4570 100644

[PATCH 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Hello, This patch series makes use of the new of_clk_parent_fill() helper function. This patch series is not intended for v4.2, as I think it's a bit late, but I just wanted to make sure people have time to test it. The series is based on

[PATCH 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Boris Brezillon boris.brezil...@free-electrons.com --- drivers/clk/at91/clk-main.c | 7 +--

[PATCH 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Hello, This patch series makes use of the new of_clk_parent_fill() helper function. This patch series is not intended for v4.2, as I think it's a bit late, but I just wanted to make sure people have time to test it. The series is based on

[PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Maxime Ripard maxime.rip...@free-electrons.com Cc: Emilio López emi...@elopez.com.ar ---

[PATCH 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- drivers/clk/clk-qoriq.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

[PATCH 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Santosh Shilimkar ssant...@kernel.org --- drivers/clk/keystone/pll.c | 3 +-- 1 file changed, 1 insertion(+), 2

[PATCH 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Peter Griffin peter.grif...@linaro.org Cc: Gabriel FERNANDEZ gabriel.fernan...@st.com --- drivers/clk/st/clk-flexgen.c

[PATCH 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Tero Kristo t-kri...@ti.com --- drivers/clk/ti/apll.c | 4 +--- drivers/clk/ti/composite.c | 4 +---

[PATCHv3 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return

[PATCHv3 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- v3: none v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git

[PATCHv3 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i);

[PATCH] EDAC, altera: wrap edac pm with a CONFIG_PM

From: Alan Tull Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen Acked-by: Borislav Petkov --- Hi Boris, Please apply this patch to your

[PATCH] EDAC, altera: wrap edac pm with a CONFIG_PM

From: Alan Tull at...@opensource.altera.com Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Signed-off-by: Alan Tull at...@opensource.altera.com Signed-off-by: Dinh Nguyen

[PATCHv3 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v3: none v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files

[PATCHv3 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen dingu...@opensource.altera.com Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code

[PATCHv3 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen dingu...@opensource.altera.com Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i num_parents; ++i) parent_names[i] =

[RFC/PATCHv2 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git

[RFC/PATCHv2 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i);

[RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return

[RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen dingu...@opensource.altera.com Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code

[RFC/PATCHv2 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen dingu...@opensource.altera.com Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i num_parents; ++i) parent_names[i] =

[RFC/PATCHv2 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2

[RFC/PATCHv1 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return

[RFC/PATCHv1 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate.c

[RFC/PATCHv1 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since this kind of code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i);

[RFC/PATCHv1 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen dingu...@opensource.altera.com Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since this kind of code is sprinkled all over the platform clock drivers: for (i = 0; i num_parents; ++i) parent_names[i] =

[RFC/PATCHv1 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen dingu...@opensource.altera.com Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code

[RFC/PATCHv1 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11

[PATCH] usb: dwc2: fix unnecessary USB overcurrent condition

From: Dinh Nguyen For platforms that use a ULPI phy, we should enable the external VbusValid signal instead. Signed-off-by: Dinh Nguyen Cc: Gregory Herrero Cc: Mian Yousaf Kaukab Cc: Felipe Balbi --- drivers/usb/dwc2/core.c | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCH] usb: dwc2: fix unnecessary USB overcurrent condition

From: Dinh Nguyen dingu...@opensource.altera.com For platforms that use a ULPI phy, we should enable the external VbusValid signal instead. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Cc: Gregory Herrero gregory.herr...@intel.com Cc: Mian Yousaf Kaukab yousaf.kau...@intel.com Cc:

[PATCH 1/3] ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5

From: Dinh Nguyen Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/platsmp.c | 2 ++ arch/arm/mach-socfpga/socfpga.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git

[PATCH 2/3] ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

From: Dinh Nguyen Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different.

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