Re: [PATCH] ASoC: wm8962: Relax bit clock divider searching

2021-03-16 Thread Mark Brown
On Wed, 3 Mar 2021 19:21:28 +0800, Shengjiu Wang wrote: > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a:

Re: [PATCH] ASoC: wm8962: Relax bit clock divider searching

2021-03-07 Thread Charles Keepax
On Wed, Mar 03, 2021 at 07:21:28PM +0800, Shengjiu Wang wrote: > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962

Re: [PATCH] ASoC: wm8962: Relax bit clock divider searching

2021-03-05 Thread Daniel Baluta
On Fri, Mar 5, 2021 at 1:15 AM Shengjiu Wang wrote: > > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a:

[PATCH] ASoC: wm8962: Relax bit clock divider searching

2021-03-03 Thread Shengjiu Wang
With S20_3LE format case, the sysclk = rate * 384, the bclk = rate * 20 * 2, there is no proper bclk divider for 384 / 40, because current condition needs exact match. So driver fails to configure the clocking: wm8962 3-001a: Unsupported BCLK ratio 9 Fix this by relaxing bitclk divider