Re: [PATCH] atmel_spi: Fix clock polarity

2008-02-23 Thread Haavard Skinnemoen
On Sat, 23 Feb 2008 00:05:07 -0800 Andrew Morton <[EMAIL PROTECTED]> wrote: > I had it queued for 2.6.26 which I guess was wrong. I'll bump it into > 2.6.25. Thanks! > Is it needed in 2.6.24.x? I think so. The last time that code was changed was before 2.6.23 AFAICT, so perhaps 2.6.23.x as

Re: [PATCH] atmel_spi: Fix clock polarity

2008-02-23 Thread Andrew Morton
On Thu, 21 Feb 2008 11:11:38 +0900 (JST) Atsushi Nemoto <[EMAIL PROTECTED]> wrote: > This patch is already in mm tree as atmel_spi-fix-clock-polarity.patch. > I just rewrite description slightly and add my signed-off and acked-by > from Haavard Skinnemoen. I had it queued for 2.6.26 which I

Re: [PATCH] atmel_spi: Fix clock polarity

2008-02-23 Thread Andrew Morton
On Thu, 21 Feb 2008 11:11:38 +0900 (JST) Atsushi Nemoto [EMAIL PROTECTED] wrote: This patch is already in mm tree as atmel_spi-fix-clock-polarity.patch. I just rewrite description slightly and add my signed-off and acked-by from Haavard Skinnemoen. I had it queued for 2.6.26 which I guess

Re: [PATCH] atmel_spi: Fix clock polarity

2008-02-23 Thread Haavard Skinnemoen
On Sat, 23 Feb 2008 00:05:07 -0800 Andrew Morton [EMAIL PROTECTED] wrote: I had it queued for 2.6.26 which I guess was wrong. I'll bump it into 2.6.25. Thanks! Is it needed in 2.6.24.x? I think so. The last time that code was changed was before 2.6.23 AFAICT, so perhaps 2.6.23.x as well.

[PATCH] atmel_spi: Fix clock polarity

2008-02-20 Thread Atsushi Nemoto
The atmel_spi driver does not initialize clock polarity correctly (except for at91rm9200 CS0 channel) in some case. The atmel_spi driver uses gpio-controlled chipselect. OTOH spi clock signal is controlled by CSRn.CPOL bit, but this register controls clock signal correctly only in 'real

[PATCH] atmel_spi: Fix clock polarity

2008-02-20 Thread Atsushi Nemoto
The atmel_spi driver does not initialize clock polarity correctly (except for at91rm9200 CS0 channel) in some case. The atmel_spi driver uses gpio-controlled chipselect. OTOH spi clock signal is controlled by CSRn.CPOL bit, but this register controls clock signal correctly only in 'real