Re: [PATCH] clk: rockchip: fix clock select order for usbphy480m_src

Am Donnerstag, 13. November 2014, 16:11:49 schrieb Kever Yang: > According to rk3288 trm, the mux selector locate at bit[12:11] > of CRU_CLKSEL13_CON shows: > 2'b00: select HOST0 USB pll clock (clk_otgphy1) > 2'b01: select HOST1 USB pll clock (clk_otgphy2) > 2'b10: select OTG USB pll clock

Re: [PATCH] clk: rockchip: fix clock select order for usbphy480m_src

Am Donnerstag, 13. November 2014, 16:11:49 schrieb Kever Yang: According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock

[PATCH] clk: rockchip: fix clock select order for usbphy480m_src

According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 -

[PATCH] clk: rockchip: fix clock select order for usbphy480m_src

According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 -