On Sat, Sep 6, 2014 at 2:21 PM, Bjorn Helgaas wrote:
>
> But as you point out, we don't see the "not responding" message. We
> only print that if we read 0x0001 (device/vendor ID). But lspci
> claims the vendor:device ID is 0001:8168. So my new theory is:
[snip]
Sounds like a very
[+cc Josh]
On Tue, Sep 2, 2014 at 1:30 PM, Linus Torvalds
wrote:
> On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas wrote:
>>
>> I'm not a fan of adding a whitelist for devices that work correctly.
>> I don't think that's a maintainable solution. Since we haven't had
>> many systems yet that care
[+cc Josh]
On Tue, Sep 2, 2014 at 1:30 PM, Linus Torvalds
torva...@linux-foundation.org wrote:
On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas bhelg...@google.com wrote:
I'm not a fan of adding a whitelist for devices that work correctly.
I don't think that's a maintainable solution. Since we
On Sat, Sep 6, 2014 at 2:21 PM, Bjorn Helgaas bhelg...@google.com wrote:
But as you point out, we don't see the not responding message. We
only print that if we read 0x0001 (device/vendor ID). But lspci
claims the vendor:device ID is 0001:8168. So my new theory is:
[snip]
Sounds like
On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas wrote:
>
> I'm not a fan of adding a whitelist for devices that work correctly.
> I don't think that's a maintainable solution. Since we haven't had
> many systems yet that care about CRS, some kind of "enable CRS on
> machines newer than X" might
Hi,
On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas wrote:
> [+cc Linus (author of ad7edfe04908), Matthew (author of 07ff9220908c
> from full history), Yinghai (author of 2f5d8e4ff947), Richard]
>
> On Thu, Aug 28, 2014 at 3:55 PM, Rajat Jain wrote:
>> The PCIe root port of the Intel Haswell CPU,
Hi,
On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas bhelg...@google.com wrote:
[+cc Linus (author of ad7edfe04908), Matthew (author of 07ff9220908c
from full history), Yinghai (author of 2f5d8e4ff947), Richard]
On Thu, Aug 28, 2014 at 3:55 PM, Rajat Jain rajatxj...@gmail.com wrote:
The PCIe
On Mon, Sep 1, 2014 at 9:14 PM, Bjorn Helgaas bhelg...@google.com wrote:
I'm not a fan of adding a whitelist for devices that work correctly.
I don't think that's a maintainable solution. Since we haven't had
many systems yet that care about CRS, some kind of enable CRS on
machines newer
[+cc Linus (author of ad7edfe04908), Matthew (author of 07ff9220908c
from full history), Yinghai (author of 2f5d8e4ff947), Richard]
On Thu, Aug 28, 2014 at 3:55 PM, Rajat Jain wrote:
> The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
> retry the configuration cycles, if
[+cc Linus (author of ad7edfe04908), Matthew (author of 07ff9220908c
from full history), Yinghai (author of 2f5d8e4ff947), Richard]
On Thu, Aug 28, 2014 at 3:55 PM, Rajat Jain rajatxj...@gmail.com wrote:
The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
retry the
On Fri, Aug 29, 2014 at 10:11:16AM -0700, Rajat Jain wrote:
>Hello Wei Yang,
>
>Thanks for your mail and review.
>
>On Thu, Aug 28, 2014 at 9:04 PM, Wei Yang wrote:
>> On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
>>>The PCIe root port of the Intel Haswell CPU, has a behavior to
On Fri, Aug 29, 2014 at 10:11:16AM -0700, Rajat Jain wrote:
Hello Wei Yang,
Thanks for your mail and review.
On Thu, Aug 28, 2014 at 9:04 PM, Wei Yang weiy...@linux.vnet.ibm.com wrote:
On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
The PCIe root port of the Intel Haswell CPU, has a
Hello Wei Yang,
Thanks for your mail and review.
On Thu, Aug 28, 2014 at 9:04 PM, Wei Yang wrote:
> On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
>>The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
>>retry the configuration cycles, if an endpoint responds
Hello Wei Yang,
Thanks for your mail and review.
On Thu, Aug 28, 2014 at 9:04 PM, Wei Yang weiy...@linux.vnet.ibm.com wrote:
On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
retry the configuration cycles, if an
On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
>The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
>retry the configuration cycles, if an endpoint responds with a CRS
>(Configuration Request Retry Status), and the "CRS Software Visibility"
>flag is not set at the
The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
retry the configuration cycles, if an endpoint responds with a CRS
(Configuration Request Retry Status), and the "CRS Software Visibility"
flag is not set at the root port. This results in a CPU hang, when the
kernel tries to
The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
retry the configuration cycles, if an endpoint responds with a CRS
(Configuration Request Retry Status), and the CRS Software Visibility
flag is not set at the root port. This results in a CPU hang, when the
kernel tries to
On Thu, Aug 28, 2014 at 02:55:25PM -0700, Rajat Jain wrote:
The PCIe root port of the Intel Haswell CPU, has a behavior to endlessly
retry the configuration cycles, if an endpoint responds with a CRS
(Configuration Request Retry Status), and the CRS Software Visibility
flag is not set at the root
18 matches
Mail list logo
