Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Palmer Dabbelt
Sorry, I missed this before submitting our v7. I'll respond properly in a bit... On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote: > On 11/07/2017 03:39, Palmer Dabbelt wrote: >> The RISC-V ISA defines a per-hart real-time clock and timer, which is >> present on all

Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Palmer Dabbelt
Sorry, I missed this before submitting our v7. I'll respond properly in a bit... On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote: > On 11/07/2017 03:39, Palmer Dabbelt wrote: >> The RISC-V ISA defines a per-hart real-time clock and timer, which is >> present on all

Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Daniel Lezcano
On 11/07/2017 03:39, Palmer Dabbelt wrote: > The RISC-V ISA defines a per-hart real-time clock and timer, which is > present on all systems. The clock is accessed via the 'rdtime' > pseudo-instruction (which reads a CSR), and the timer is set via an SBI > call. > > This driver attempts to split

Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Daniel Lezcano
On 11/07/2017 03:39, Palmer Dabbelt wrote: > The RISC-V ISA defines a per-hart real-time clock and timer, which is > present on all systems. The clock is accessed via the 'rdtime' > pseudo-instruction (which reads a CSR), and the timer is set via an SBI > call. > > This driver attempts to split

[PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-11 Thread Palmer Dabbelt
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the

[PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-11 Thread Palmer Dabbelt
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the

[PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-10 Thread Palmer Dabbelt
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the

[PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-10 Thread Palmer Dabbelt
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the