Sorry, I missed this before submitting our v7. I'll respond properly in a
bit...
On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote:
> On 11/07/2017 03:39, Palmer Dabbelt wrote:
>> The RISC-V ISA defines a per-hart real-time clock and timer, which is
>> present on all
Sorry, I missed this before submitting our v7. I'll respond properly in a
bit...
On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote:
> On 11/07/2017 03:39, Palmer Dabbelt wrote:
>> The RISC-V ISA defines a per-hart real-time clock and timer, which is
>> present on all
On 11/07/2017 03:39, Palmer Dabbelt wrote:
> The RISC-V ISA defines a per-hart real-time clock and timer, which is
> present on all systems. The clock is accessed via the 'rdtime'
> pseudo-instruction (which reads a CSR), and the timer is set via an SBI
> call.
>
> This driver attempts to split
On 11/07/2017 03:39, Palmer Dabbelt wrote:
> The RISC-V ISA defines a per-hart real-time clock and timer, which is
> present on all systems. The clock is accessed via the 'rdtime'
> pseudo-instruction (which reads a CSR), and the timer is set via an SBI
> call.
>
> This driver attempts to split
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
This driver attempts to split out the RISC-V ISA specific mechanisms of
accessing the
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
This driver attempts to split out the RISC-V ISA specific mechanisms of
accessing the
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
This driver attempts to split out the RISC-V ISA specific mechanisms of
accessing the
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
This driver attempts to split out the RISC-V ISA specific mechanisms of
accessing the
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