Re: [PATCH 09/15] riscv: provide native clint access for M-mode

On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig wrote: > > RISC-V has the concept of a cpu level interrupt controller. The > interface for it is split between a standardized part that is exposed > as bits in the mstatus/sstatus register and the mie/mip/sie/sip > CRS. But the bit to actually

[PATCH 09/15] riscv: provide native clint access for M-mode

RISC-V has the concept of a cpu level interrupt controller. The interface for it is split between a standardized part that is exposed as bits in the mstatus/sstatus register and the mie/mip/sie/sip CRS. But the bit to actually trigger IPIs is not standardized and just mentioned as implementable