Re: [PATCH 1/2] x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata

2019-06-27 Thread Ricardo Neri
On Thu, Jun 27, 2019 at 10:38:13PM +0200, Thomas Gleixner wrote: > Ricardo, > > On Thu, 27 Jun 2019, Ricardo Neri wrote: > > > > +/* > > + * Processors which have self-snooping capability can handle conflicting > > + * memory type across CPUs by snooping its own cache. However, there exists > >

Re: [PATCH 1/2] x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata

2019-06-27 Thread Thomas Gleixner
Ricardo, On Thu, 27 Jun 2019, Ricardo Neri wrote: > > +/* > + * Processors which have self-snooping capability can handle conflicting > + * memory type across CPUs by snooping its own cache. However, there exists > + * CPU models in which having conflicting memory types still leads to > + *

[PATCH 1/2] x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata

2019-06-27 Thread Ricardo Neri
Processors which have self-snooping capability can handle conflicting memory type across CPUs by snooping its own cache. However, there exists CPU models in which having conflicting memory types still leads to unpredictable behavior, machine check errors, or hangs. Clear this feature to prevent