Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Vignesh R
On Thursday 10 August 2017 05:38 AM, Rob Herring wrote: > On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: >> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >> Controller programming sequence, a delay equal to couple QSPI master >> clock(~5ns) is required after

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Vignesh R
On Thursday 10 August 2017 05:38 AM, Rob Herring wrote: > On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: >> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >> Controller programming sequence, a delay equal to couple QSPI master >> clock(~5ns) is required after

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Vignesh R
On Thursday 10 August 2017 05:35 AM, Rob Herring wrote: > On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: >> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >> Controller programming sequence, a delay equal to couple QSPI master >> clock(~5ns) is required after

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Vignesh R
On Thursday 10 August 2017 05:35 AM, Rob Herring wrote: > On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: >> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access >> Controller programming sequence, a delay equal to couple QSPI master >> clock(~5ns) is required after

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Rob Herring
On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: > As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access > Controller programming sequence, a delay equal to couple QSPI master > clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and > writing data to the

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Rob Herring
On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: > As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access > Controller programming sequence, a delay equal to couple QSPI master > clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and > writing data to the

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Rob Herring
On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: > As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access > Controller programming sequence, a delay equal to couple QSPI master > clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and > writing data to the

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-09 Thread Rob Herring
On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote: > As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access > Controller programming sequence, a delay equal to couple QSPI master > clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and > writing data to the

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-07-31 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Add a new compatible to handle the couple of cycles of delay

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-07-31 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Add a new compatible to handle the couple of cycles of delay