On Wed, Sep 04, 2013 at 08:47:16PM +0200, Alexander Gordeev wrote:
> On Wed, Sep 04, 2013 at 02:06:07PM -0400, Tejun Heo wrote:
> > I don't think it's necessary / a good idea to try to support
> > everything. Just following the spec would be fine. If that doesn't
> > work for too many devices,
On Wed, Sep 04, 2013 at 02:06:07PM -0400, Tejun Heo wrote:
> I don't think it's necessary / a good idea to try to support
> everything. Just following the spec would be fine. If that doesn't
> work for too many devices, maybe just do one fallback?
Calling pci_enable_msi_block_part() in a loop
Hello,
On Wed, Sep 04, 2013 at 06:14:43PM +0200, Alexander Gordeev wrote:
> 1. We do not support sharing MSI messages since there is no appropriate
> interrupt handling for it. I am not sure if any hardware supports it at
> all. This assumption is just for clarity here.
I don't think it even
On Wed, Sep 04, 2013 at 10:55:59AM -0400, Tejun Heo wrote:
> Hello,
>
> On Wed, Sep 04, 2013 at 09:22:57AM +0200, Alexander Gordeev wrote:
> > I think a general approach that will cover it all (including ICH and
> > undesired
> > sharing of interrupt vectors) - start MME from
Hello,
On Wed, Sep 04, 2013 at 09:22:57AM +0200, Alexander Gordeev wrote:
> I think a general approach that will cover it all (including ICH and undesired
> sharing of interrupt vectors) - start MME from roundup_pow_of_two(n_ports) and
> ensure MRSM bit is unset. If not - double MME and retry. If
On Tue, Sep 03, 2013 at 02:27:31PM -0400, Tejun Heo wrote: > Hello,
>
> On Tue, Sep 03, 2013 at 06:19:06PM +0200, Alexander Gordeev wrote:
> > We must enable maximum possible number of MSIs - the one reported in
> > Multiple Message Capable register. Otherwise ICH device will fallback
> > to
On Tue, Sep 03, 2013 at 02:27:31PM -0400, Tejun Heo wrote: Hello,
On Tue, Sep 03, 2013 at 06:19:06PM +0200, Alexander Gordeev wrote:
We must enable maximum possible number of MSIs - the one reported in
Multiple Message Capable register. Otherwise ICH device will fallback
to MRSM. IOW, if
Hello,
On Wed, Sep 04, 2013 at 09:22:57AM +0200, Alexander Gordeev wrote:
I think a general approach that will cover it all (including ICH and undesired
sharing of interrupt vectors) - start MME from roundup_pow_of_two(n_ports) and
ensure MRSM bit is unset. If not - double MME and retry. If
On Wed, Sep 04, 2013 at 10:55:59AM -0400, Tejun Heo wrote:
Hello,
On Wed, Sep 04, 2013 at 09:22:57AM +0200, Alexander Gordeev wrote:
I think a general approach that will cover it all (including ICH and
undesired
sharing of interrupt vectors) - start MME from roundup_pow_of_two(n_ports)
Hello,
On Wed, Sep 04, 2013 at 06:14:43PM +0200, Alexander Gordeev wrote:
1. We do not support sharing MSI messages since there is no appropriate
interrupt handling for it. I am not sure if any hardware supports it at
all. This assumption is just for clarity here.
I don't think it even
On Wed, Sep 04, 2013 at 02:06:07PM -0400, Tejun Heo wrote:
I don't think it's necessary / a good idea to try to support
everything. Just following the spec would be fine. If that doesn't
work for too many devices, maybe just do one fallback?
Calling pci_enable_msi_block_part() in a loop may
On Wed, Sep 04, 2013 at 08:47:16PM +0200, Alexander Gordeev wrote:
On Wed, Sep 04, 2013 at 02:06:07PM -0400, Tejun Heo wrote:
I don't think it's necessary / a good idea to try to support
everything. Just following the spec would be fine. If that doesn't
work for too many devices, maybe
Hello,
On Tue, Sep 03, 2013 at 06:19:06PM +0200, Alexander Gordeev wrote:
> We must enable maximum possible number of MSIs - the one reported in
> Multiple Message Capable register. Otherwise ICH device will fallback
> to MRSM. IOW, if the result of roundup_pow_of_two(n_ports) is not what
> in
On Tue, Sep 03, 2013 at 10:18:24AM -0400, Tejun Heo wrote:
> On Mon, Sep 02, 2013 at 11:00:28AM +0200, Alexander Gordeev wrote:
> > + if (hpriv->flags & AHCI_HFLAG_NO_MSI)
> > + goto intx;
> > +
> > + rc = pci_enable_msi_block_part(pdev, n_ports, AHCI_MAX_PORTS);
We start with
On Mon, Sep 02, 2013 at 11:00:28AM +0200, Alexander Gordeev wrote:
> + if (hpriv->flags & AHCI_HFLAG_NO_MSI)
> + goto intx;
> +
> + rc = pci_enable_msi_block_part(pdev, n_ports, AHCI_MAX_PORTS);
> + if (!rc)
> + return AHCI_MAX_PORTS;
> + if (rc < 0)
> +
On Mon, Sep 02, 2013 at 11:00:28AM +0200, Alexander Gordeev wrote:
+ if (hpriv-flags AHCI_HFLAG_NO_MSI)
+ goto intx;
+
+ rc = pci_enable_msi_block_part(pdev, n_ports, AHCI_MAX_PORTS);
+ if (!rc)
+ return AHCI_MAX_PORTS;
+ if (rc 0)
+
On Tue, Sep 03, 2013 at 10:18:24AM -0400, Tejun Heo wrote:
On Mon, Sep 02, 2013 at 11:00:28AM +0200, Alexander Gordeev wrote:
+ if (hpriv-flags AHCI_HFLAG_NO_MSI)
+ goto intx;
+
+ rc = pci_enable_msi_block_part(pdev, n_ports, AHCI_MAX_PORTS);
We start with maximum possible
Hello,
On Tue, Sep 03, 2013 at 06:19:06PM +0200, Alexander Gordeev wrote:
We must enable maximum possible number of MSIs - the one reported in
Multiple Message Capable register. Otherwise ICH device will fallback
to MRSM. IOW, if the result of roundup_pow_of_two(n_ports) is not what
in
Make use of the new pci_enable_msi_block_part() interface
and conserve on othewise wasted interrupt resources for 10
of 16 unused MSI vectors on Intel chipsets.
Signed-off-by: Alexander Gordeev
---
drivers/ata/ahci.c | 48 +---
1 files changed, 29
Make use of the new pci_enable_msi_block_part() interface
and conserve on othewise wasted interrupt resources for 10
of 16 unused MSI vectors on Intel chipsets.
Signed-off-by: Alexander Gordeev agord...@redhat.com
---
drivers/ata/ahci.c | 48 +---
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