Re: [PATCH 8/9] perf intel-pt: Update documentation about itrace G and L options

> > > > On Skylake/Goldmont the PEBS event contains the TSC and the time stamp > > reported by > > perf should report the time the event was sampled based on that TSC. > > Or is that not working for some reason? > > I guess it is not working like that, but perf tools would probably need >

Re: [PATCH 8/9] perf intel-pt: Update documentation about itrace G and L options

On 30/04/20 2:03 am, Andi Kleen wrote: >> +One caveat with the G and L options is that they work poorly with "Large >> PEBS". >> +Large PEBS means PEBS records will be accumulated by hardware and the >> written >> +into the event buffer in one go. That reduces interrupts, but can give very >>

Re: [PATCH 8/9] perf intel-pt: Update documentation about itrace G and L options

> +One caveat with the G and L options is that they work poorly with "Large > PEBS". > +Large PEBS means PEBS records will be accumulated by hardware and the written > +into the event buffer in one go. That reduces interrupts, but can give very > +late timestamps. Because the Intel PT trace is

[PATCH 8/9] perf intel-pt: Update documentation about itrace G and L options

Provide a little more information about the new G and L options, particularly the issue with large PEBs. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/itrace.txt| 4 +++ tools/perf/Documentation/perf-intel-pt.txt | 35 ++ 2 files changed, 39