Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-07-02 Thread Rajneesh Bhardwaj
On Mon, Jul 02, 2018 at 03:19:22PM +0300, Andy Shevchenko wrote: > On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj > wrote: > > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: > >> From: > >> > >> Adds debugfs access to registers in the Cannonlake PCH PMC that are > >> useful

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-07-02 Thread Rajneesh Bhardwaj
On Mon, Jul 02, 2018 at 03:19:22PM +0300, Andy Shevchenko wrote: > On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj > wrote: > > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: > >> From: > >> > >> Adds debugfs access to registers in the Cannonlake PCH PMC that are > >> useful

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-07-02 Thread Andy Shevchenko
On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj wrote: > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: >> From: >> >> Adds debugfs access to registers in the Cannonlake PCH PMC that are >> useful for debugging #SLP_S0 signal assertion and other low power >> related activities.

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-07-02 Thread Andy Shevchenko
On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj wrote: > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: >> From: >> >> Adds debugfs access to registers in the Cannonlake PCH PMC that are >> useful for debugging #SLP_S0 signal assertion and other low power >> related activities.

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-15 Thread Rajneesh Bhardwaj
On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: > From: > > Adds debugfs access to registers in the Cannonlake PCH PMC that are > useful for debugging #SLP_S0 signal assertion and other low power > related activities. Device pm states are latched in these registers > whenever the

Re: [PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-15 Thread Rajneesh Bhardwaj
On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote: > From: > > Adds debugfs access to registers in the Cannonlake PCH PMC that are > useful for debugging #SLP_S0 signal assertion and other low power > related activities. Device pm states are latched in these registers > whenever the

[PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-14 Thread David E. Box
From: Adds debugfs access to registers in the Cannonlake PCH PMC that are useful for debugging #SLP_S0 signal assertion and other low power related activities. Device pm states are latched in these registers whenever the package enters C10 and can be read from slp_s0_debug_status. The pm states

[PATCH V4] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-14 Thread David E. Box
From: Adds debugfs access to registers in the Cannonlake PCH PMC that are useful for debugging #SLP_S0 signal assertion and other low power related activities. Device pm states are latched in these registers whenever the package enters C10 and can be read from slp_s0_debug_status. The pm states