> On 06/22/2013 09:10 PM, Huacai Chen wrote:
>>
>> Is the 3rd patch of V10 is OK to be accepted now? If so, could the
>> patchset of V10 be merged into 3.11?
>>
> The merge window for 3.11 is closed at this point. You should get it
> prepared for 3.12, so start tracking the 'mips-for-linux-next'
On 06/22/2013 09:10 PM, Huacai Chen wrote:
Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?
The merge window for 3.11 is closed at this point. You should get it
prepared for 3.12, so start tracking the 'mips-for-linux-next' branch
with
On 06/22/2013 09:10 PM, Huacai Chen wrote:
Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?
The merge window for 3.11 is closed at this point. You should get it
prepared for 3.12, so start tracking the 'mips-for-linux-next' branch
with
On 06/22/2013 09:10 PM, Huacai Chen wrote:
Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?
The merge window for 3.11 is closed at this point. You should get it
prepared for 3.12, so start tracking the 'mips-for-linux-next' branch
with
Hi, Steven
Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?
Huacai
On Fri, Apr 12, 2013 at 11:07 AM, Huacai Chen wrote:
> Hi, Steven,
>
> Maybe you are misunderstand Loongson-3's "hardware-maintained cache".
> Loongson-3's hardware
Hi, Steven
Is the 3rd patch of V10 is OK to be accepted now? If so, could the
patchset of V10 be merged into 3.11?
Huacai
On Fri, Apr 12, 2013 at 11:07 AM, Huacai Chen che...@lemote.com wrote:
Hi, Steven,
Maybe you are misunderstand Loongson-3's hardware-maintained cache.
Loongson-3's
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 01/30/2013 12:24 AM, Huacai Chen wrote:
> Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
> feature named cpu_has_coherent_cache and use it to modify MIPS's cache
> flushing functions.
>
> Signed-off-by: Huacai Chen
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 01/30/2013 12:24 AM, Huacai Chen wrote:
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen
Signed-off-by: Hongliang Tao
Signed-off-by: Hua Yan
---
arch/mips/include/asm/cacheflush.h
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
10 matches
Mail list logo