Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh

On Fri, May 31, 2019 at 1:40 PM Palmer Dabbelt wrote: > > On Thu, 30 May 2019 15:29:22 PDT (-0700), luke.r.n...@gmail.com wrote: > > In BPF, 32-bit ALU operations should zero-extend their results into > > the 64-bit registers. > > > > The current BPF JIT on RISC-V emits incorrect instructions

Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh

On Thu, 30 May 2019 15:29:22 PDT (-0700), luke.r.n...@gmail.com wrote: In BPF, 32-bit ALU operations should zero-extend their results into the 64-bit registers. The current BPF JIT on RISC-V emits incorrect instructions that perform sign extension only (e.g., addw, subw) on 32-bit add, sub,

Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh

On Fri, 31 May 2019 at 01:08, Song Liu wrote: > > On Thu, May 30, 2019 at 3:30 PM Luke Nelson wrote: > > > > In BPF, 32-bit ALU operations should zero-extend their results into > > the 64-bit registers. > > > > The current BPF JIT on RISC-V emits incorrect instructions that perform > > sign

Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh

On Thu, May 30, 2019 at 3:30 PM Luke Nelson wrote: > > In BPF, 32-bit ALU operations should zero-extend their results into > the 64-bit registers. > > The current BPF JIT on RISC-V emits incorrect instructions that perform > sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh, >

[PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh

In BPF, 32-bit ALU operations should zero-extend their results into the 64-bit registers. The current BPF JIT on RISC-V emits incorrect instructions that perform sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh, arsh, and neg. This behavior diverges from the interpreter and