Re: [PATCH v02 2/5] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX

> This patch introduces it for wrmsrl's done for testing LBR support. > Future patch in series adds the quirk for context switch, that would > be required if LBR callstack is to be enabled for ring 0. Patches are fine for me. Reviewed-by: Andi Kleen -Andi

Re: [PATCH v02 2/5] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX

> This patch introduces it for wrmsrl's done for testing LBR support. > Future patch in series adds the quirk for context switch, that would > be required if LBR callstack is to be enabled for ring 0. Patches are fine for me. Reviewed-by: Andi Kleen -Andi

[PATCH v02 2/5] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX

Intel's SDM states that bits 61:62 in MSR_LAST_BRANCH_FROM_x are the TSX flags for formats with LBR_TSX flags (i.e. LBR_FORMAT_EIP_EFLAGS2). However, when the CPU has TSX support deactivated, bits 61:62 actually behave as follows: - For wrmsr, bits 61:62 are considered part of the sign

[PATCH v02 2/5] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX

Intel's SDM states that bits 61:62 in MSR_LAST_BRANCH_FROM_x are the TSX flags for formats with LBR_TSX flags (i.e. LBR_FORMAT_EIP_EFLAGS2). However, when the CPU has TSX support deactivated, bits 61:62 actually behave as follows: - For wrmsr, bits 61:62 are considered part of the sign