On Sat, Apr 16, 2016 at 12:03:39PM +0100, Gabriele Paoloni wrote:
> Currently dw_pcie_setup_rc configures memory base and memory
> limit in the type1 configuration header for the root complex.
> In doing so it uses the cpu address (pp->mem_base) rather than
> the bus address (pp->mem_bus_addr):
On Sat, Apr 16, 2016 at 12:03:39PM +0100, Gabriele Paoloni wrote:
> Currently dw_pcie_setup_rc configures memory base and memory
> limit in the type1 configuration header for the root complex.
> In doing so it uses the cpu address (pp->mem_base) rather than
> the bus address (pp->mem_bus_addr):
On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni
wrote:
>
> Currently dw_pcie_setup_rc configures memory base and memory
> limit in the type1 configuration header for the root complex.
> In doing so it uses the cpu address (pp->mem_base) rather than
> the bus address
On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni
wrote:
>
> Currently dw_pcie_setup_rc configures memory base and memory
> limit in the type1 configuration header for the root complex.
> In doing so it uses the cpu address (pp->mem_base) rather than
> the bus address (pp->mem_bus_addr): this is
Currently dw_pcie_setup_rc configures memory base and memory
limit in the type1 configuration header for the root complex.
In doing so it uses the cpu address (pp->mem_base) rather than
the bus address (pp->mem_bus_addr): this is wrong and it is
useless since the configuration is overwritten later
Currently dw_pcie_setup_rc configures memory base and memory
limit in the type1 configuration header for the root complex.
In doing so it uses the cpu address (pp->mem_base) rather than
the bus address (pp->mem_bus_addr): this is wrong and it is
useless since the configuration is overwritten later
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