Re: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-26 Thread Bjorn Helgaas
On Sat, Apr 16, 2016 at 12:03:39PM +0100, Gabriele Paoloni wrote: > Currently dw_pcie_setup_rc configures memory base and memory > limit in the type1 configuration header for the root complex. > In doing so it uses the cpu address (pp->mem_base) rather than > the bus address (pp->mem_bus_addr):

Re: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-26 Thread Bjorn Helgaas
On Sat, Apr 16, 2016 at 12:03:39PM +0100, Gabriele Paoloni wrote: > Currently dw_pcie_setup_rc configures memory base and memory > limit in the type1 configuration header for the root complex. > In doing so it uses the cpu address (pp->mem_base) rather than > the bus address (pp->mem_bus_addr):

Re: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-19 Thread Pratyush Anand
On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni wrote: > > Currently dw_pcie_setup_rc configures memory base and memory > limit in the type1 configuration header for the root complex. > In doing so it uses the cpu address (pp->mem_base) rather than > the bus address

Re: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-19 Thread Pratyush Anand
On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni wrote: > > Currently dw_pcie_setup_rc configures memory base and memory > limit in the type1 configuration header for the root complex. > In doing so it uses the cpu address (pp->mem_base) rather than > the bus address (pp->mem_bus_addr): this is

[PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-16 Thread Gabriele Paoloni
Currently dw_pcie_setup_rc configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the cpu address (pp->mem_base) rather than the bus address (pp->mem_bus_addr): this is wrong and it is useless since the configuration is overwritten later

[PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration

2016-04-16 Thread Gabriele Paoloni
Currently dw_pcie_setup_rc configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the cpu address (pp->mem_base) rather than the bus address (pp->mem_bus_addr): this is wrong and it is useless since the configuration is overwritten later