On Sat, May 27, 2017 at 07:08:34PM +0300, Andy Shevchenko wrote:
> On Fri, May 26, 2017 at 7:09 PM, Mika Westerberg
> wrote:
> > The DMA (NHI) port of a switch provides access to the NVM of the host
> > controller (and devices starting from Intel Alpine Ridge).
On Sat, May 27, 2017 at 07:08:34PM +0300, Andy Shevchenko wrote:
> On Fri, May 26, 2017 at 7:09 PM, Mika Westerberg
> wrote:
> > The DMA (NHI) port of a switch provides access to the NVM of the host
> > controller (and devices starting from Intel Alpine Ridge). The NVM
> > contains also more
On Fri, May 26, 2017 at 7:09 PM, Mika Westerberg
wrote:
> The DMA (NHI) port of a switch provides access to the NVM of the host
> controller (and devices starting from Intel Alpine Ridge). The NVM
> contains also more complete DROM for the root switch including
On Fri, May 26, 2017 at 7:09 PM, Mika Westerberg
wrote:
> The DMA (NHI) port of a switch provides access to the NVM of the host
> controller (and devices starting from Intel Alpine Ridge). The NVM
> contains also more complete DROM for the root switch including vendor
> and device identification
The DMA (NHI) port of a switch provides access to the NVM of the host
controller (and devices starting from Intel Alpine Ridge). The NVM
contains also more complete DROM for the root switch including vendor
and device identification strings.
This will look for the DMA port capability for each
The DMA (NHI) port of a switch provides access to the NVM of the host
controller (and devices starting from Intel Alpine Ridge). The NVM
contains also more complete DROM for the root switch including vendor
and device identification strings.
This will look for the DMA port capability for each
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