Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Tue, Jun 20, 2017 at 10:22:17PM -0700, Andy Lutomirski wrote: > PCID is a "process context ID" -- it's what other architectures call > an address space ID. Every non-global TLB entry is tagged with a > PCID, only TLB entries that match the currently selected PCID are > used, and we can switch

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Tue, Jun 20, 2017 at 10:22:17PM -0700, Andy Lutomirski wrote: > PCID is a "process context ID" -- it's what other architectures call > an address space ID. Every non-global TLB entry is tagged with a > PCID, only TLB entries that match the currently selected PCID are > used, and we can switch

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, 22 Jun 2017, Andy Lutomirski wrote: > On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner wrote: > > On Thu, 22 Jun 2017, Andy Lutomirski wrote: > >> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner > >> wrote: > >> > Now one other optimization which

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, 22 Jun 2017, Andy Lutomirski wrote: > On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner wrote: > > On Thu, 22 Jun 2017, Andy Lutomirski wrote: > >> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner > >> wrote: > >> > Now one other optimization which should be trivial to add is to keep the

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner wrote: > On Thu, 22 Jun 2017, Andy Lutomirski wrote: >> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: >> > Now one other optimization which should be trivial to add is to keep the 4 >> > asid

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner wrote: > On Thu, 22 Jun 2017, Andy Lutomirski wrote: >> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: >> > Now one other optimization which should be trivial to add is to keep the 4 >> > asid context entries in cpu_tlbstate and cache the

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, 22 Jun 2017, Andy Lutomirski wrote: > On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: > > Now one other optimization which should be trivial to add is to keep the 4 > > asid context entries in cpu_tlbstate and cache the last asid in thread > > info. If that's

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, 22 Jun 2017, Andy Lutomirski wrote: > On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: > > Now one other optimization which should be trivial to add is to keep the 4 > > asid context entries in cpu_tlbstate and cache the last asid in thread > > info. If that's still valid then use

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: > On Wed, 21 Jun 2017, Andy Lutomirski wrote: >> On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: >> > That requires a conditional branch >> > >> > if (asid >= NR_DYNAMIC_ASIDS) { >> >

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: > On Wed, 21 Jun 2017, Andy Lutomirski wrote: >> On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: >> > That requires a conditional branch >> > >> > if (asid >= NR_DYNAMIC_ASIDS) { >> > asid = 0; >> >

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 9:09 AM, Nadav Amit wrote: > Andy Lutomirski wrote: > >> >> --- a/arch/x86/mm/init.c >> +++ b/arch/x86/mm/init.c >> @@ -812,6 +812,7 @@ void __init zone_sizes_init(void) >> >> DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state,

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Thu, Jun 22, 2017 at 9:09 AM, Nadav Amit wrote: > Andy Lutomirski wrote: > >> >> --- a/arch/x86/mm/init.c >> +++ b/arch/x86/mm/init.c >> @@ -812,6 +812,7 @@ void __init zone_sizes_init(void) >> >> DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { >> .loaded_mm = _mm, >>

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

Andy Lutomirski wrote: > > --- a/arch/x86/mm/init.c > +++ b/arch/x86/mm/init.c > @@ -812,6 +812,7 @@ void __init zone_sizes_init(void) > > DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { > .loaded_mm = _mm, > + .next_asid = 1, I think this is a

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

Andy Lutomirski wrote: > > --- a/arch/x86/mm/init.c > +++ b/arch/x86/mm/init.c > @@ -812,6 +812,7 @@ void __init zone_sizes_init(void) > > DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { > .loaded_mm = _mm, > + .next_asid = 1, I think this is a remainder from

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, 21 Jun 2017, Andy Lutomirski wrote: > On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: > > That requires a conditional branch > > > > if (asid >= NR_DYNAMIC_ASIDS) { > > asid = 0; > > > > } > > > > The

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, 21 Jun 2017, Andy Lutomirski wrote: > On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: > > That requires a conditional branch > > > > if (asid >= NR_DYNAMIC_ASIDS) { > > asid = 0; > > > > } > > > > The question is whether 4 IDs

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: > On Tue, 20 Jun 2017, Andy Lutomirski wrote: >> This patch uses PCID differently. We use a PCID to identify a >> recently-used mm on a per-cpu basis. An mm has no fixed PCID >> binding at all; instead, we give it a

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote: > On Tue, 20 Jun 2017, Andy Lutomirski wrote: >> This patch uses PCID differently. We use a PCID to identify a >> recently-used mm on a per-cpu basis. An mm has no fixed PCID >> binding at all; instead, we give it a fresh PCID each time

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, 21 Jun 2017, Thomas Gleixner wrote: > > + for (asid = 0; asid < NR_DYNAMIC_ASIDS; asid++) { > > + if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) != > > + next->context.ctx_id) > > + continue; > > + > > + *new_asid = asid; > > +

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Wed, 21 Jun 2017, Thomas Gleixner wrote: > > + for (asid = 0; asid < NR_DYNAMIC_ASIDS; asid++) { > > + if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) != > > + next->context.ctx_id) > > + continue; > > + > > + *new_asid = asid; > > +

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Tue, 20 Jun 2017, Andy Lutomirski wrote: > This patch uses PCID differently. We use a PCID to identify a > recently-used mm on a per-cpu basis. An mm has no fixed PCID > binding at all; instead, we give it a fresh PCID each time it's > loaded except in cases where we want to preserve the TLB,

Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

On Tue, 20 Jun 2017, Andy Lutomirski wrote: > This patch uses PCID differently. We use a PCID to identify a > recently-used mm on a per-cpu basis. An mm has no fixed PCID > binding at all; instead, we give it a fresh PCID each time it's > loaded except in cases where we want to preserve the TLB,

[PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

PCID is a "process context ID" -- it's what other architectures call an address space ID. Every non-global TLB entry is tagged with a PCID, only TLB entries that match the currently selected PCID are used, and we can switch PGDs without flushing the TLB. x86's PCID is 12 bits. This is an

[PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID

PCID is a "process context ID" -- it's what other architectures call an address space ID. Every non-global TLB entry is tagged with a PCID, only TLB entries that match the currently selected PCID are used, and we can switch PGDs without flushing the TLB. x86's PCID is 12 bits. This is an