Re: [PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

2019-02-28 Thread Honghui Zhang
On Thu, 2019-02-28 at 17:42 +, Lorenzo Pieralisi wrote: > On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The PCIE_AXI_WINDOW0 defines the translate window size for the request > > from EP side. Request outside of this window will

Re: [PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

2019-02-28 Thread Lorenzo Pieralisi
On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang > > The PCIE_AXI_WINDOW0 defines the translate window size for the request > from EP side. Request outside of this window will be treated as > unsupported request. > > Enlarge this window size from

[PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

2019-01-31 Thread honghui.zhang
From: Honghui Zhang The PCIE_AXI_WINDOW0 defines the translate window size for the request from EP side. Request outside of this window will be treated as unsupported request. Enlarge this window size from fls(0x) to 2^33 to support 8GB translate address range then EP DMA is capable of