[PATCH v3 2/2] iio: Aspeed ADC

Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold interrupts are supported by the hardware but are not currently implemented. Signed-off-by: Rick Altherr --- Changes in v3: - Drop model numbers from description as same IP is used in every generation -

[PATCH v3 2/2] iio: Aspeed ADC

Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold interrupts are supported by the hardware but are not currently implemented. Signed-off-by: Rick Altherr --- Changes in v3: - Drop model numbers from description as same IP is used in every generation - Remove unused macros