Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-07 Thread Andre Przywara
Hi, On 05/09/16 10:58, Suzuki K Poulose wrote: > Right now we trap some of the user space data cache operations > based on a few Errata (ARM 819472, 826319, 827319 and 824069). > We need to trap userspace access to CTR_EL0, if we detect mismatched > cache line size. Since both these traps share

Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-07 Thread Andre Przywara
Hi, On 05/09/16 10:58, Suzuki K Poulose wrote: > Right now we trap some of the user space data cache operations > based on a few Errata (ARM 819472, 826319, 827319 and 824069). > We need to trap userspace access to CTR_EL0, if we detect mismatched > cache line size. Since both these traps share

Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-07 Thread Will Deacon
On Mon, Sep 05, 2016 at 10:58:28AM +0100, Suzuki K Poulose wrote: > Right now we trap some of the user space data cache operations > based on a few Errata (ARM 819472, 826319, 827319 and 824069). > We need to trap userspace access to CTR_EL0, if we detect mismatched > cache line size. Since both

Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-07 Thread Will Deacon
On Mon, Sep 05, 2016 at 10:58:28AM +0100, Suzuki K Poulose wrote: > Right now we trap some of the user space data cache operations > based on a few Errata (ARM 819472, 826319, 827319 and 824069). > We need to trap userspace access to CTR_EL0, if we detect mismatched > cache line size. Since both

[PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-05 Thread Suzuki K Poulose
Right now we trap some of the user space data cache operations based on a few Errata (ARM 819472, 826319, 827319 and 824069). We need to trap userspace access to CTR_EL0, if we detect mismatched cache line size. Since both these traps share the EC, refactor the handler a little bit to make it a

[PATCH v3 8/9] arm64: Refactor sysinstr exception handling

2016-09-05 Thread Suzuki K Poulose
Right now we trap some of the user space data cache operations based on a few Errata (ARM 819472, 826319, 827319 and 824069). We need to trap userspace access to CTR_EL0, if we detect mismatched cache line size. Since both these traps share the EC, refactor the handler a little bit to make it a