Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Suzuki K Poulose
On 05/09/16 11:10, Ard Biesheuvel wrote: On 5 September 2016 at 10:58, Suzuki K Poulose wrote: +/* + * read_ctr - read CTR_EL0. If the system has mismatched + * cache line sizes, provide the system wide safe value. + */ + .macro read_ctr, reg +alternative_if_not

Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Suzuki K Poulose
On 05/09/16 11:10, Ard Biesheuvel wrote: On 5 September 2016 at 10:58, Suzuki K Poulose wrote: +/* + * read_ctr - read CTR_EL0. If the system has mismatched + * cache line sizes, provide the system wide safe value. + */ + .macro read_ctr, reg +alternative_if_not

Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Ard Biesheuvel
On 5 September 2016 at 10:58, Suzuki K Poulose wrote: > Systems with differing CPU i-cache/d-cache line sizes can cause > problems with the cache management by software when the execution > is migrated from one to another. Usually, the application reads > the cache size on

Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Ard Biesheuvel
On 5 September 2016 at 10:58, Suzuki K Poulose wrote: > Systems with differing CPU i-cache/d-cache line sizes can cause > problems with the cache management by software when the execution > is migrated from one to another. Usually, the application reads > the cache size on a CPU and then uses

[PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Suzuki K Poulose
Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application reads the cache size on a CPU and then uses that length to perform cache operations. However, if it gets

[PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-05 Thread Suzuki K Poulose
Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application reads the cache size on a CPU and then uses that length to perform cache operations. However, if it gets