On 2/22/24 18:06, maobibo wrote:
On 2024/2/22 下午5:34, WANG Xuerui wrote:
On 2/17/24 11:15, maobibo wrote:
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks
for providing microbenchmark numbers! But
On 2024/2/22 下午5:34, WANG Xuerui wrote:
On 2/17/24 11:15, maobibo wrote:
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks
for providing microbenchmark numbers! But it seems the more
comprehensive
On 2/17/24 11:15, maobibo wrote:
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks for
providing microbenchmark numbers! But it seems the more comprehensive
CoreMark results were omitted (that's also
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks for
providing microbenchmark numbers! But it seems the more comprehensive
CoreMark results were omitted (that's also absent in v3)? While the
Of
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks for
providing microbenchmark numbers! But it seems the more comprehensive
CoreMark results were omitted (that's also absent in v3)? While the
Of course the benchmark suite should be
Hi,
On 2/1/24 11:19, Bibo Mao wrote:
[snip]
Here is the microbenchmarck data with perf bench futex wake case on 3C5000
single-way machine, there are 16 cpus on 3C5000 single-way machine, VM
has 16 vcpus also. The benchmark data is ms time unit to wakeup 16 threads,
the performance is higher if
This patchset adds pv ipi support for VM. On physical machine, ipi HW
uses IOCSR registers, however there is trap into hypervisor when vcpu
accesses IOCSR registers if system is in VM mode. SWI is a interrupt
mechanism like SGI on ARM, software can send interrupt to CPU, only that
on LoongArch SWI
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