On Mon, Mar 29, 2021 at 01:41:28PM +0800, Like Xu wrote:
> + if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) {
> + if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) {
> + pmu->pebs_enable_mask = ~pmu->global_ctrl;
> +
On Mon, Mar 29, 2021 at 01:41:28PM +0800, Like Xu wrote:
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 546d6ecf0a35..9afcad882f4f 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -186,6 +186,12 @@
>
If IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14] is set, the
IA32_PEBS_ENABLE MSR exists and all architecturally enumerated fixed
and general purpose counters have corresponding bits in IA32_PEBS_ENABLE
that enable generation of PEBS records. The general-purpose counter bits
start at bit
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