On Mon, Feb 25, 2019 at 5:35 PM Ley Foon Tan wrote:
>
> On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> > On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> > >
> > > Add PCIe Root Port support for Stratix 10 device.
> > >
> > > Main differences:
> > Main differences
On Tue, 2019-02-19 at 16:23 +, Lorenzo Pieralisi wrote:
> On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> >
> > Add PCIe Root Port support for Stratix 10 device.
> >
> > Main differences:
> Main differences with what ? We need to rewrite this commit log.
Differences compare
On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device.
>
> Main differences:
Main differences with what ? We need to rewrite this commit log.
> - HIP interface to access Root Port configuration register.
> - TLP programming flow:
> -
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
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drivers/pci/controller/pcie-altera.c | 246
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