On 2014/8/13 0:25, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space
> and instead use a range of CPU addresses that map to bus addresses.
> For some architectures these ranges will be expressed by OF bindings
> in a device tree file.
>
> This patch introduces
On 2014/8/13 0:25, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree file.
This patch introduces a
On Tue, Aug 12, 2014 at 11:25 AM, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space
> and instead use a range of CPU addresses that map to bus addresses.
> For some architectures these ranges will be expressed by OF bindings
> in a device tree file.
>
> This
On Tue, Aug 12, 2014 at 11:25 AM, Liviu Dudau liviu.du...@arm.com wrote:
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree
On Mon, Aug 18, 2014 at 10:34:46PM +0100, Liviu Dudau wrote:
> On Mon, Aug 18, 2014 at 03:26:04PM +0100, Catalin Marinas wrote:
> > On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
> > > Some architectures do not have a simple view of the PCI I/O space
> > > and instead use a range of
On Mon, Aug 18, 2014 at 03:26:04PM +0100, Catalin Marinas wrote:
> On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
> > Some architectures do not have a simple view of the PCI I/O space
> > and instead use a range of CPU addresses that map to bus addresses.
> > For some architectures
On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space
> and instead use a range of CPU addresses that map to bus addresses.
> For some architectures these ranges will be expressed by OF bindings
> in a device tree file.
>
On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree file.
This
On Mon, Aug 18, 2014 at 03:26:04PM +0100, Catalin Marinas wrote:
On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these
On Mon, Aug 18, 2014 at 10:34:46PM +0100, Liviu Dudau wrote:
On Mon, Aug 18, 2014 at 03:26:04PM +0100, Catalin Marinas wrote:
On Tue, Aug 12, 2014 at 05:25:16PM +0100, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree file.
This patch introduces a pci_register_io_range() helper function with
a
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree file.
This patch introduces a pci_register_io_range() helper function with
a
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