On Mon, Mar 03, 2014 at 09:38:03AM +, Shevchenko, Andriy wrote:
> > + if (IS_ERR(bdev->bamclk))
> > + return PTR_ERR(bdev->bamclk);
> > +
> > + ret = clk_prepare_enable(bdev->bamclk);
> > + if (ret) {
> > + dev_err(bdev->dev, "failed to prepare/enable clock\n");
>
On Sat, Mar 08, 2014 at 12:29:49AM +0200, Stanimir Vabanov wrote:
> > +#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
> > +#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
>
> s/pipe/ee ?
>
Ah good catch. I'll fix that.
> > +struct bam_chan {
> > + struct
Hi Andy,
Thanks for the patch.
> +#define BAM_IRQ_SRCS_EE(pipe)(0x0800 + ((pipe) * 0x80))
> +#define BAM_IRQ_SRCS_MSK_EE(pipe)(0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
> +struct bam_chan {
> + struct virt_dma_chan vc;
> +
> + struct bam_device *bdev;
> +
> + /*
Hi Andy,
Thanks for the patch.
snip
+#define BAM_IRQ_SRCS_EE(pipe)(0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe)(0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
snip
+struct bam_chan {
+ struct virt_dma_chan vc;
+
+ struct bam_device *bdev;
+
+ /*
On Sat, Mar 08, 2014 at 12:29:49AM +0200, Stanimir Vabanov wrote:
+#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
Ah good catch. I'll fix that.
+struct bam_chan {
+ struct
On Mon, Mar 03, 2014 at 09:38:03AM +, Shevchenko, Andriy wrote:
snip
+ if (IS_ERR(bdev-bamclk))
+ return PTR_ERR(bdev-bamclk);
+
+ ret = clk_prepare_enable(bdev-bamclk);
+ if (ret) {
+ dev_err(bdev-dev, failed to prepare/enable clock\n);
+
On Mon, 2014-03-03 at 00:30 -0600, Andy Gross wrote:
> Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
> found in the MSM 8x74 platforms.
>
> Each BAM DMA device is associated with a specific on-chip peripheral. Each
> channel provides a uni-directional data
On Mon, 2014-03-03 at 00:30 -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer
On Mon, 2014-03-03 at 00:30 -0600, Andy Gross wrote:
> Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
> found in the MSM 8x74 platforms.
>
> Each BAM DMA device is associated with a specific on-chip peripheral. Each
> channel provides a uni-directional data
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the
On Mon, 2014-03-03 at 00:30 -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer
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